// Clock generation for Mixed Signal Simulations
// Dan Yeager, 2008
// University of Washington
// Wireless Sensing Lab

`timescale 1ns/1ns

module clk_gen ( tag_clk, reader_clk);

  output tag_clk, reader_clk;

  reg tag_clk, reader_clk;

  // clock period in ns
  parameter T_CLK_TAG    = 250; // 4 mhz
  parameter T_CLK_READER = 128; // roughly 8mhz

  initial // Clock generator for tag
    begin
      tag_clk = 0;
      #(T_CLK_TAG / 2) 
      forever begin
        #(T_CLK_TAG / 2) tag_clk = !tag_clk;
      end
    end
    
  initial // Clock generator for reader
    begin
      reader_clk = 0;
      #(T_CLK_READER/2) 
      forever begin
        #(T_CLK_READER/2) reader_clk = !reader_clk;
      end
    end


endmodule