// mux_tb.v

// 4x1 MUX

// ------------------------------------------------------------------
// Copyright (c) 2006 Susan Lysecky, University of Arizona
// Permission to copy is granted provided that this header remains
// intact. This software is provided with no warranties.
// ------------------------------------------------------------------

`timescale 1ns / 1ps

module Testbench;

   reg [3:0] Input0_t, Input1_t, Input2_t, Input3_t;
   reg [2:0] Sel_t;
   wire [3:0] Data_out_t; 

   Mux Mux_1(Input0_t, Input1_t, Input2_t, Input3_t, Sel_t, Data_out_t);
   
   initial
   begin

      // assign values to input register
      Input0_t <= 0;
      Input1_t <= 1;
      Input2_t <= 2;
      Input3_t <= 3;

      //case 0 - Input0 value should be display on output
      Sel_t <= 0;
      #1 $display("Data_out_t = %b", Data_out_t);
	  
      //case 1 - Input1 value should be display on output
      Sel_t <= 1;
      #1 $display("Data_out_t = %b", Data_out_t);

      //case 2 - Input2 value should be display on output
      Sel_t <= 2;
      #1 $display("Data_out_t = %b", Data_out_t);

      //case 3 - Input3 value should be display on output
      Sel_t <= 3;
      #1 $display("Data_out_t = %b", Data_out_t);

      // reassign value to input register Input0 and display on output
      Input0_t = 8;
      Sel_t <= 0;
      #1 $display("Data_out_t = %b", Data_out_t);

      // reassign value to input register Input0 and display on output
      Input0_t = 4;
      Sel_t <= 0;
      #1 $display("Data_out_t = %b", Data_out_t);
		
   end
endmodule