library verilog;
use verilog.vl_types.all;
entity Mux is
    generic(
        S0              : vl_logic_vector(0 to 1) := (Hi0, Hi0);
        S1              : vl_logic_vector(0 to 1) := (Hi0, Hi1);
        S2              : vl_logic_vector(0 to 1) := (Hi1, Hi0);
        S3              : vl_logic_vector(0 to 1) := (Hi1, Hi1)
    );
    port(
        Input0          : in     vl_logic_vector(3 downto 0);
        Input1          : in     vl_logic_vector(3 downto 0);
        Input2          : in     vl_logic_vector(3 downto 0);
        Input3          : in     vl_logic_vector(3 downto 0);
        Sel             : in     vl_logic_vector(1 downto 0);
        Data_out        : out    vl_logic_vector(3 downto 0)
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of S0 : constant is 1;
    attribute mti_svvh_generic_type of S1 : constant is 1;
    attribute mti_svvh_generic_type of S2 : constant is 1;
    attribute mti_svvh_generic_type of S3 : constant is 1;
end Mux;