module mux4x1_test (d3,d2,d1,d0, sel, out);
input out;
output d3,d2,d1,d0;
output [1:0] sel;
reg d3,d2,d1,d0;
reg [1:0] sel;
initial
  begin

  d0 <= 1'b0;
  d1 <= 1'b1;
  d0 <= 1'b1;
  d1 <= 1'b0;
  d2 <= 1'b1;
  d3 <= 1'b0;
  sel <= 2'd0;
  #100;
  sel <= 2'd1;
  #100;
  sel <= 2'd2;
  #100;
  sel <= 2'd3;
  #100;

  d0 <= 1'b1;
  d1 <= 1'b1;
  d2 <= 1'b0;
  d3 <= 1'b1;
  sel <= 2'd0;
  #100;
  sel <= 2'd1;
  #100;
  sel <= 2'd2;
  #100;
  sel <= 2'd3;
  #100;
  
  end
endmodule


module mux4x1_bench ();
wire [1:0] sel;
mux4x1_test tester (d3, d2, d1, d0, sel, out);

mux4x1 mux0 (d3, d2, d1, d0, sel, out);
endmodule


module mux4bit(a, s, o);

input [3:0] a;

input [1:0] s;

output o;

reg o;

always @(a or s)

begin

case (s)

2'b00:o=a[0];

2'b01: o=a[1];

2'b10: o=a[2];

2'b11: o=a[3];

default: o=0;

endcase

end

endmodule


module muxt_b;

reg [3:0] a;

reg [1:0] s;

wire o;

mux4bit uut (.a(a),   .s(s),.o(o));

initial begin

#10 a=4'b1010;

#10 s=2'b00;

#10 s=2'b01;

#10 s=2'b10;

#10 s=2'b11;

#10 $stop;

end

endmodule

/******************************************************************************************/

// 3 vers 8 
module decoder (input reg [2:0] in,
                output reg [7:0] o);
                
                
          always @ (in)
          
              case (in)
              0: o = 8'b00000001;
              1: o = 8'b00000010;
              2: o = 8'b00000100;
              3: o = 8'b00001000;
              4: o = 8'b00010000;
              5: o = 8'b00100000;
              6: o = 8'b01000000;
              7: o = 8'b10000000;
              
              
            endcase

endmodule

            
module decoder_bench;

    reg [2:0] in;
    wire [7:0] o;
 
    decoder uut ( .in(in), .o(o) );
  
    initial begin
      
    in = 0;
    
    #100;
    in = 3'b001;
    #100;
    in = 3'b010;
    #100;
     in = 3'b011;
    #100;
     in = 3'b100;
    #100;
     in = 3'b101;
    #100;
     in = 3'b110;
    #100;
     in = 3'b111;
    #100;
        
    end  


endmodule

// avec une clock
module decoder_bis;

    reg [2:0] in;
    wire [7:0] o;
 
    decoder uut ( .in(in), .o(o) );
  
    reg clk_50M;
    
    always
    begin
      clk_50M = 0;
      #10;
      clk_50M = 1;
      #10;
     end
    
     initial begin
      
    in = 0;
    
    #100;
    in = 3'b001;
    #100;
    in = 3'b010;
    #100;
     in = 3'b011;
    #100;
     in = 3'b100;
    #100;
     in = 3'b101;
    #100;
     in = 3'b110;
    #100;
     in = 3'b111;
    #100;
        
    end   
 


endmodule