library verilog;
use verilog.vl_types.all;
entity clock_div is
    generic(
        period          : integer := 10;
        half_period     : vl_notype
    );
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        clk_out         : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of period : constant is 1;
    attribute mti_svvh_generic_type of half_period : constant is 3;
end clock_div;