`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:31:29 12/01/2013 
// Design Name: 
// Module Name:    code 
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// Target Devices: 
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// Description: 
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// Dependencies: 
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// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//NET "Clk" LOC = "C9";
//NET "Rst" LOC = "K17" | PULLDOWN;
//NET "DivRst" LOC = "D18" | PULLDOWN;

//NET "Enable" LOC = "N17";
//NET "Short" LOC = "H18";

module LEDblink(clk, LED);
input clk;     // clock typically from 10MHz to 50MHz
output LED;

// create a binary counter
reg [32:0] cnt;
always @(posedge clk) cnt<=cnt+1;

assign LED = cnt[22];    // blink the LED at a few Hz (change the bit index to change the blinking rate)
endmodule


module ClkDiv(Clk, Rst, ClkOut);

   input Clk, Rst;
   output reg ClkOut;
  
   parameter DivVal = 25000000;
   reg[24:0] DivCnt;
   reg ClkInt;
	
   always @(posedge Clk) begin
      if( Rst == 1 )begin
         DivCnt <= 0;
         ClkOut <= 0;
         ClkInt <= 0;
      end
      else begin
         if( DivCnt == DivVal ) begin
            ClkOut <= ~ClkInt;
            ClkInt <= ~ClkInt;
            DivCnt <= 0;
         end
         else begin
            ClkOut <= ClkInt;
            ClkInt <= ClkInt;
            DivCnt <= DivCnt + 1;
         end
      end
   end
endmodule