`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    11:22:25 12/08/2013 
// Design Name: 
// Module Name:    bench 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ns
`include "./diviseur.v"
module bench;
    reg RESET,F10M;
    wire F500K;
    always #10 F10M=~F10M;
    initial
    begin
   F10M=0;
   RESET=1;
    #10 RESET=0;
    #100 RESET=1;
    #10000 $stop;
end
diviseur m(.RESET(RESET),.F10M(F10M),.F500K(F500K));
endmodule