`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    11:21:22 12/08/2013 
// Design Name: 
// Module Name:    diviseur 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module diviseur(RESET,F10M,F500K);
input F10M,RESET;
output F500K;
reg F500K;
reg [7:0]j;
  always @(posedge F10M)
    if(!RESET)          //??????
      begin
        F500K <= 0;
        j <= 0;
      end
    else 
      begin
        if(j==19)      //????????????F500K???????
          begin
            j <= 0;
            F500K <= ~F500K;
          end
        else
          j <= j+1;
      end
endmodule


module clock_out(cin, cout);
input cin;
output cout;
reg cout;
reg [27:0]CLKQ; //clock divider register
reg Clock; 

always@(posedge cin)
begin
	CLKQ<=CLKQ+1; //clock divider register
	if (CLKQ==25000000) //1 Hz Output Clock: 50 MHz Master
		begin // Clock 25x10^6 half-cycle count
		Clock=~Clock; //Output Clock
		CLKQ<=0; //reset clock divider register
		cout=~cout; //toggle DIIE LED ON/OFF
		end
end
endmodule 


// horloge 50Mhz soit une période de 20ns
/* pour un délai de 5ms, il faut 50ms/20ns = 250000 cycle d'horloge */
/* il faut concevoir un compteur modulo 250000 */
/* soit un compteur de 18 bit car 2 puissance 18 = 252144*/ 

module tp(input clk, output led0);

reg [23:0] cnt = 0;

always@(posedge clk)
	cnt <= cnt + 1;
	
	assign led0 = cnt[23];

endmodule

//http://therobotfix.wordpress.com/2011/06/27/getting-started-with-spartan-3e-fpga-and-verilog/

module blink(
	clk,	// clock signal
	ledpin	// LED pin
    );

	// inputs and outputs
	input clk;

	output ledpin;
	reg ledpin = 0;	

	// internal variable
	reg [25:0] counter = 50_000_000;	// 26 bit variable

	always @(posedge clk)
	if (counter == 0) begin			// at 1 second
		counter <= 50_000_000;		// reset counter
		ledpin <= !ledpin;		// invert ledpin
	end else begin
		counter <= counter - 1;		// decrease
	end

endmodule