| diviseur Project Status | |||
| Project File: | diviseur.xise | Parser Errors: | No Errors |
| Module Name: | diviseur | Implementation State: | New (Failed) |
| Target Device: | xc3s500e-4fg320 |
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| Product Version: | ISE 14.5 |
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| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: |
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| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | ||||||
| Translation Report | ||||||
| Map Report | ||||||
| Place and Route Report | ||||||
| Power Report | ||||||
| Post-PAR Static Timing Report | ||||||
| Bitgen Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Out of Date | dim. 8. déc. 11:24:45 2013 | |