 module progdiv(clk,rst,clk1Hz);

parameter WIDTH=25;   // default 25-bit counter

input clk;                                            // 50MHz

input rst;

output clk1Hz;

reg clk1Hz;

  reg [WIDTH-1:0] cnt;

always @(posedge clk, posedge rst)

begin

  if (rst) begin

     cnt <= 0;

     clk1Hz <= 0;

  end else if (cnt == 25000000) begin

     cnt <= 0;                                        // wrap around

     clk1Hz <= ~clk1Hz;    // toggle

  end else begin

     cnt <= cnt + 1;

  end

end 