1)indiquer le schematic top_dig
-cellname
-libname

2)listing des ports

3)netlist topcell 
si port en commun avec top dig -> archivage

4) classement de la netlit par bloc


http://www.cadence.com/Community/blogs/cic/archive/2011/05/03/skill-for-the-skilled-sorting-with-skill.aspx

http://www.youtube.com/watch?v=81WBV0E6sqA

http://fr.scribd.com/doc/61606469/CadenceIC61%E7%94%A8%E6%B3%95

Pin optimization is done to position pins of blocks in a manner that helps obtain the shortest possible net length 
at a particular level in the design. 
Pin optimization must be done even for blocks that are placed by the Block Placer because the aggregate length of nets 
connecting pins of the blocks may not be optimal or the shortest. Pin optimization should be done before routing the design. 


largeur edgeseal
hauteur edgeseal

x_top_left_boundary
y_top_left_boundary

x_top_right_boundary
y_top_right_boundary

x_bottom_left_boundary
y_bottom_left_boundary

x_bottom_right_boundary
y_bottom_right_boundary





xancre_pin_absolu
yancre_pin_absolu

