module d_ff(clk, D, Q, Q_bar);

	//inputs
	input clk, D;
	//outputs
	output Q, Q_bar;
	reg Q, Q_bar;

	always @ (posedge clk) begin

	if (D == 1) begin
	Q = 1;
	Q_bar = 0;
	end
	if (D == 0) begin
	Q = 0;
	Q_bar = 1;
	end
	end
	endmodule

//Test benchmark for test_1
module d_ff_tb;

	reg clk, D;
	wire Q, Q_bar;
	initial begin
	$monitor("D=%b,Q=%b,Q_bar=%b", D, Q, Q_bar);
	clk = 0;
	#5 D = 0;
	#5 D = 1;
	#10 $finish;
end

//Test benchmark for test_1
module d_ff_tb;
	
	reg clk, D;
	wire Q, Q_bar;
	initial begin
	$monitor("D=%b,Q=%b,Q_bar=%b", D, Q, Q_bar);
	clk = 0;
	#5 D = 0;
	#5 D = 1;
	#10 $finish;
	end

	always begin
	#5clk = !clk;
	end

	d_ff U0 (clk, D, Q, Q_bar);

endmodule