module testbed();
reg c_in;
reg [3:0] y;
reg [3:0] x;
wire c_out;
wire [3:0]sum;
FourBitAdder A1(sum, c_out, x, y, c_in);
Initial
begin
x = 4'b0001; y = 4'b0001; c_in = 1'b0;
#25 x = 4'b0001; y = 4'b0010;
#25 x = 4'b0010; y = 4'b0011;
#25 x = 4'b0001; y = 4'b1111;
#25 x = 4'b0001; y = 4'b1111; c_in = 1'b1;
#25 x = 4'b1000; y = 4'b1111; c_in = 1'b0;
#25 x = 4'b0001; y = 4'b0001; c_in = 1'b1;
#25 x = 4'b0001; y = 4'b0010;
#25 x = 4'b0010; y = 4'b0011;
#25 x = 4'b0011; y = 4'b1111;
#25;
end
initial
#250 $finish;
endmodule