Host command: /IUS820/tools/verilog/bin/verilog.exe Command arguments: test.v essai.v Tool: VERILOG-XL 08.20.001-p log file created Jul 24, 2011 11:48:20 Tool: VERILOG-XL 08.20.001-p Jul 24, 2011 11:48:20 Copyright (c) 1995-2004 Cadence Design Systems, Inc. All Rights Reserved. Unpublished -- rights reserved under the copyright laws of the United States. Copyright (c) 1995-2004 UNIX Systems Laboratories, Inc. Reproduced with Permission. THIS SOFTWARE AND ON-LINE DOCUMENTATION CONTAIN CONFIDENTIAL INFORMATION AND TRADE SECRETS OF CADENCE DESIGN SYSTEMS, INC. USE, DISCLOSURE, OR REPRODUCTION IS PROHIBITED WITHOUT THE PRIOR EXPRESS WRITTEN PERMISSION OF CADENCE DESIGN SYSTEMS, INC. RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013 or subparagraphs (c)(1) and (2) of Commercial Computer Software -- Restricted Rights at 48 CFR 52.227-19, as applicable. Cadence Design Systems, Inc. 555 River Oaks Parkway San Jose, California 95134 For technical assistance please contact the Cadence Response Center at 1-877-CDS-4911 or send email to support@cadence.com For more information on Cadence's Verilog-XL product line send email to talkv@cadence.com Compiling source file "test.v" Compiling source file "essai.v" Highest level modules: stimulus At Time: 5 Accumulator Output= x At Time: 10 Accumulator Output= 0 At Time: 15 Accumulator Output= 0 At Time: 20 Accumulator Output= 1 At Time: 25 Accumulator Output= 1 At Time: 30 Accumulator Output= 2 At Time: 35 Accumulator Output= 2 At Time: 40 Accumulator Output= 3 At Time: 45 Accumulator Output= 3 L21 "test.v": $finish at simulation time 50 0 simulation events (use +profile or +listcounts option to count) CPU time: 0.1 secs to compile + 0.0 secs to link + 0.0 secs in simulation End of Tool: VERILOG-XL 08.20.001-p Jul 24, 2011 11:48:20