module clk_divider( input clk, input rst, output reg slow_clk ); reg [23:0] cnt; reg led; assign cnt_done = (cnt == 24'd2500000); always @(posedge clk or posedge rst) if (rst) cnt <= 0; else if (cnt_done) cnt <= 0; else cnt <= cnt + 1; always @(posedge clk or posedge rst) if (rst) led <= 0; else if (cnt_done) led <= ~led; endmodule