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/////////////////////////////////////////////////////

module real_time_clk_verilog (clk,reset,hour1,hour2,minute1,minute2,second1,second2, hr_A2, min_A1, sec_A0, load, data_in);

input clk,reset;
output reg [6:0]hour1,hour2,minute1,minute2,second1,second2;
input load;
input hr_A2,min_A1,sec_A0;
input [7:0]data_in;reg clk_sec,clk_msec;
reg [7:0]sec,min,hr;
integer timer_count1=0,timer_count2=0;

always@(posedge clk)

begin
  if(timer_count1==3999)
  begin
  timer_count1=0;
  clk_msec=1'b1;
  end
  else
  begin
  timer_count1=timer_count1+1;
  clk_msec=1'b0;
  end
  end
  always@(posedge clk_msec)
  begin
  if(timer_count2==999)
  begin
  timer_count2=0;
  clk_sec=1'b1;
  end
  else
  begin
  timer_count2=timer_count2+1;
  clk_sec=1'b0;
  end
  end
  
  always@(negedge clk_sec)
  begin
  if(~reset)
  begin
  sec=0;
  min=0;
  hr=0;
  end
  else
  if(~load)
  begin
  if(hr_A2)
  begin
  if(hr[7:4] == 4'b0010)
  begin
  if(hr[3:0] < 4'b0100)
  hr = data_in;
  end

else if(hr[7:4] < 4'b0010)
  hr = data_in;
  else
  hr = 8'b0;
  end
  
  if(min_A1)
  begin
  
  if(min[7:4] < 4'b0110)
  min = data_in;
  else
  min = 8'b0;
  end
  if(sec_A0)
  begin
  if (sec[7:4] < 4'b0110)
  sec = data_in;
  else
  sec = 8'b0;
  end
  end
  else
  begin
  if(sec[3:0]==4'b1001)
  begin
  sec[3:0]=4'b0;
  if(sec[7:4]==4'b0101)
  begin
  sec[7:4]=4'b0;
  if(min[3:0]==4'b1001)
  begin
  min[3:0]=4'b0;
  if(min[7:4]==4'b0101)
  begin
  min[7:4]=4'b0;
  if(hr==8'b00100011)
  hr=0;
  else
  if(hr[3:0]==4'b1001)
  begin
  hr[3:0]=4'b0;
  hr[7:4]=hr[7:4]+1;
  end
  
  else

hr[3:0]=hr[3:0]+1; //hours count completed 
  
  end
  else
  min[7:4]=min[7:4]+1;
  end
  else
  min[3:0]=min[3:0]+1; // minutes countcompleted
  
  end
  else
  sec[7:4]=sec[7:4]+1;
  end
  else
  sec[3:0]=sec[3:0]+1; //seconds count completed
  end
  end
  
  always@(sec)
				begin
				case (sec[3:0])
				4'b0000: second1=7'b1111110;
				4'b0001: second1=7'b0110000;
				4'b0010: second1=7'b1101101;
				4'b0011: second1=7'b1111001;
				4'b0100: second1=7'b0110011;
				4'b0101: second1=7'b1011011;
				4'b0110: second1=7'b1011111;
				4'b0111: second1=7'b1110000;
				4'b1000: second1=7'b1111111;
				4'b1001: second1=7'b1111011;
				default: second1=7'b0;
				endcase
			end
			
			always@(sec)
				begin
				case(sec[7:4])
				4'b0000: second2=7'b1111110;
				4'b0001: second2=7'b0110000;
				4'b0010: second2=7'b1101101;
				4'b0011: second2=7'b1111001;
				4'b0100: second2=7'b0110011;
				4'b0101: second2=7'b1011011;
				4'b0110: second2=7'b1011111;
				4'b0111: second2=7'b1110000;
				4'b1000: second2=7'b1111111;
			  4'b1001: second2=7'b1111011;
				default: second2=7'b0;
			    endcase
			end

always@(min)
				begin
				case(min[3:0])
				4'b0000: minute1=7'b1111110;
				4'b0001: minute1=7'b0110000;
				4'b0010: minute1=7'b1101101;
				4'b0011: minute1=7'b1111001;
				4'b0100: minute1=7'b0110011;
				4'b0101: minute1=7'b1011011;
				4'b0110: minute1=7'b1011111;
				4'b0111: minute1=7'b1110000;
				4'b1000: minute1=7'b1111111;
				4'b1001: minute1=7'b1111011;
				default: minute1=7'b0;
				endcase
			end
			
			always@(min)
				begin
				case(min[7:4])
				4'b0000: minute2=7'b1111110;
				4'b0001: minute2=7'b0110000;
				4'b0010: minute2=7'b1101101;
				4'b0011: minute2=7'b1111001;
				4'b0100: minute2=7'b0110011;
				4'b0101: minute2=7'b1011011;
				4'b0110: minute2=7'b1011111;
				4'b0111: minute2=7'b1110000;
				4'b1000: minute2=7'b1111111;
				4'b1001: minute2=7'b1111011;
				default: minute2=7'b0;
				endcase
			end

always@(hr)
				begin
				case(hr[3:0])
				4'b0000: hour1=7'b1111110;
				4'b0001: hour1=7'b0110000;
				4'b0010: hour1=7'b1101101;
				4'b0011: hour1=7'b1111001; 
				4'b0100: hour1=7'b0110011;
				4'b0101: hour1=7'b1011011;
				4'b0110: hour1=7'b1011111;
				4'b0111: hour1=7'b1110000;
				4'b1000: hour1=7'b1111111;
				4'b1001: hour1=7'b1111011;
				default: hour1=7'b1111110;
				endcase
			end

always@(hr)
				begin
				case(hr[7:4])
				4'b0000: hour2=7'b1111110;
				4'b0001: hour2=7'b0110000;
				4'b0010: hour2=7'b1101101;
				default: hour2=7'b1111110;
				endcase
			end

endmodule
////////////////////////////////////////////////////
module slow_clock(real_clk,slow_clk);
  
input real_clk;
output slow_clk;
  
parameter MSB = 24;

reg [MSB:0] count;

initial count = 0;

always @(posedge real_clk)
count = count + 1;

assign slow_clk = count[MSB];

endmodule

module test();

reg real_clk;
reg [0:6] char;
wire slow_clk;
reg[6:0] count9;

slow_clock(real_clk,slow_clk);
  
  always @(posedge slow_clk)
  begin
    count9 = count9 + 1;
    if(count9 == 10)
      begin
        count9 = 0;
    end
end    
   
   assign char = 
            count9 == 0?7'b1111110: // 0
            count9 == 1?7'b0110000: // 1 
            count9 == 2?7'b1101101: // 2 
            count9 == 3?7'b1111001: // 3
            count9 == 4?7'b0110011: // 4
            count9 == 5?7'b1011011: // 5 
            count9 == 6?7'b1011111: // 6
            count9 == 7?7'b1110000: // 7
            count9 == 8?7'b1111111: // 8
            count9 == 9?7'b1111011: // 9
                        7'b1001111; // E
             
  initial
   begin
   real_clk = 1'b1;              
   end
  
    always #10 real_clk = ~real_clk;
  
  
endmodule

///////////////////////////////////////////////
module real_time_clk(clk,reset,hour1,hour2,minute1,minute2,second1,second2, 
hr_A2, min_A1, sec_A0, load, data_in);

input clk,reset;
output reg [6:0]hour1,hour2,minute1,minute2,second1,second2;
input load;
input hr_A2,min_A1,sec_A0;
input [7:0]data_in;reg clk_sec,clk_ms;
reg [7:0]sec,min,hr;

integer timer_counter1=0,timer_counter2=0;

/*always @(posedge clk)
		
		begin
			if(timer_counter1 == 2) // 3999
				begin
					timer_counter1 = 0;
					clk_ms = 1'b1;
				end	
			else
				begin 
					timer_counter1 = timer_counter1 + 1;
					clk_ms = 1'b0;
				end		
		end
				
		always @(posedge clk_ms)
		
		begin
			if(timer_counter2 == 2) // 999
				begin
					timer_counter2 = 0;
					clk_sec = 1'b1;
				end	
			else
				begin 
					timer_counter2 = timer_counter2 + 1;
					clk_sec = 1'b0;
				end		
		end		
				
		always @(posedge clk_sec)
		*/
		
		always @(posedge clk)
				
		begin
		
			if(~reset)
				begin
					sec = 0;
					min = 0;
					hr = 0;
				end
		    else
			
			if(~load)
			 
				begin
				   $display($time, " << Starting the Simulation >>");
					if(hr_A2)
						begin
							if(hr[7:4] == 4'b0010)
								begin
									if(hr[3:0] < 4'b0100)
									   hr = data_in;
								end
							else if(hr[7:4] < 4'b0010)
									hr = data_in;
									else
									hr = 8'b0;
						end			
									
					if(min_A1)
						begin
							if(min[7:4] < 4'b0110)
									min = data_in;
									else
									min = 8'b0;
						end
				
						if(sec_A0)
						begin
							if(min[7:4] < 4'b0110)
									min = data_in;
									else
									sec = 1'b0;
						end
				end
				
			else

begin
					
					if(sec[3:0] == 4'b1001)
						begin		
							sec[3:0] = 4'b0;
							if(sec[7:4] == 4'b0101)
								begin
								sec[7:4] = 4'b0;
								if(min[3:0] == 4'b0101)
								begin
									min[3:0] = 4'b0;
									if(min[7:4] == 4'b1001)
										begin
											min[7:4] = 4'b0;	
											if(hr == 8'b00100011)
											hr = 0;
											else if(hr[3:0] == 4'b1001)
											begin
												hr[3:0] = 4'b0;
												hr[7:4] = hr[7:4] +1 ;
											end	
				                    else
											hr[3:0] = hr[3:0] + 1;
									end
									else
											min[7:4] = hr[7:4] + 1;
							    end
								else
											min[3:0] = min[3:0] + 1;
								end
								else
											sec[7:4] = sec[7:4] + 1;
								end
								else
								
								sec[3:0] = sec[3:0] + 1;

end
			end

always@(sec)
				begin
				case (sec[3:0])
				4'b0000: second1=7'b1111110;
				4'b0001: second1=7'b0110000;
				4'b0010: second1=7'b1101101;
				4'b0011: second1=7'b1111001;
				4'b0100: second1=7'b0110011;
				4'b0101: second1=7'b1011011;
				4'b0110: second1=7'b1011111;
				4'b0111: second1=7'b1110000;
				4'b1000: second1=7'b1111111;
				4'b1001: second1=7'b1111011;
				default: second1=7'b0;
				endcase
			end
			
			always@(sec)
				begin
				case(sec[7:4])
				4'b0000: second2=7'b1111110;
				4'b0001: second2=7'b0110000;
				4'b0010: second2=7'b1101101;
				4'b0011: second2=7'b1111001;
				4'b0100: second2=7'b0110011;
				4'b0101: second2=7'b1011011;
				4'b0110: second2=7'b1011111;
				4'b0111: second2=7'b1110000;
				4'b1000: second2=7'b1111111;
			  4'b1001: second2=7'b1111011;
				default: second2=7'b0;
			    endcase
			end

always@(hr)
				begin
				case(hr[7:4])
				4'b0000: hour2=7'b1111110;
				4'b0001: hour2=7'b0110000;
				4'b0010: hour2=7'b1101101;
				default: hour2=7'b1111110;
				endcase
			end

endmodule

module eval_rtc();

reg               clk;
   reg               reset;
  
   
   wire [6:0]hour1,hour2,minute1,minute2,second1,second2;
   
   
   reg  load;
 
   real_time_clk_verilog DUT( .clk(clk),
                      .reset(reset), 
                      .hour1(hour1),
                      .hour2(hour2),
                      .minute1(minute1),
                      .minute2(minute2),
                      .second1(second1),
                      .second2(second2), 
                      .hr_A2(hr_A2), 
                      .min_A1(min_A1), 
                      .sec_A0(sec_A0), 
                      .load(load), 
                      .data_in(data_in));
   
//   clk,reset,hour1,hour2,minute1,minute2,second1,second2, 
//hr_A2, min_A1, sec_A0, load, data_in);
  
  
   
   initial
   begin
   clk = 1'b1;              
   reset = 1'b0;
   #10
   reset = 1'b0;
   load = 1'b0;
   end
  
    always #10 clk = ~clk;
  
endmodule  
//module real_time_clk(clk,reset,hour1,hour2,minute1,minute2,second1,second2, 
//hr_A2, min_A1, sec_A0, load, data_in);