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m255
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cModel Technology
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T_opt
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Z2 04 5 4 work manip fast 0
Z3 =1-000ae431a4f1-4e289318-18a-1d58
Z4 o-quiet -auto_acc_if_foreign -work work +acc
Z5 n@_opt
Z6 OE;O;10.0b;49
Z7 dC:\FPGA\VERILOG\DERIVE
T_opt1
Z8 VD6eTG]lbEJmLN7>m8KKjR1
Z9 04 8 4 work eval_rtc fast 0
Z10 =1-0013d417ed13-4e306443-2d0-1884
Z11 o-quiet -auto_acc_if_foreign -work work
Z12 n@_opt1
R6
R7
T_opt2
Z13 Vo>BfO[:356S0X3i`2ghW^3
R9
Z14 =2-0013d417ed13-4e305e2f-36c-1ef8
R4
Z15 n@_opt2
R6
R7
vcounter
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Z17 I2^_`4zfNI0KNaZR>LlHL?0
Z18 V>O3ULLzPCOR6ie_KW9b?f2
Z19 dC:\FPGA\VERILOG\EXO1
Z20 w1311272038
Z21 8C:/FPGA/VERILOG/EXO1/counter.v
Z22 FC:/FPGA/VERILOG/EXO1/counter.v
L0 3
Z23 OE;L;10.0b;49
r1
!s85 0
31
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Z24 !s90 -reportprogress|300|-work|work|-vopt|-nocovercells|C:/FPGA/VERILOG/EXO1/counter.v|
Z25 !s102 -nocovercells
Z26 o-work work -nocovercells -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPF
vcounter_testbench
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R19
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Z30 8C:/FPGA/VERILOG/EXO1/counter_testbench.v
Z31 FC:/FPGA/VERILOG/EXO1/counter_testbench.v
L0 11
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r1
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Z32 !s90 -reportprogress|300|-work|work|-vopt|-nocovercells|C:/FPGA/VERILOG/EXO1/counter_testbench.v|
R25
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Z33 !s107 C:/FPGA/VERILOG/EXO1/counter_testbench.v|
Z34 !s100 k32P5gNA8`2o=E?W^TDf<3
Z35 !s108 1311272043.738000
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veval_rtc
Z36 IRZ;L6@8fFXGDVJ<8imL9`1
Z37 V=lh2b=mBD@WOc4lKK<Jc:3
R19
Z38 w1311792662
Z39 8C:/FPGA/VERILOG/EXO1/rtc.v
Z40 FC:/FPGA/VERILOG/EXO1/rtc.v
Z41 L0 232
R23
r1
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Z42 !s108 1311792669.860000
Z43 !s107 C:/FPGA/VERILOG/EXO1/rtc.v|
Z44 !s90 -reportprogress|300|-work|work|-vopt|-nocovercells|C:/FPGA/VERILOG/EXO1/rtc.v|
R25
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Z45 !s100 TQU@J`=?RfFCC5lOm]IC<0
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vhex_test
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R19
Z48 w1311716313
Z49 8C:/FPGA/VERILOG/EXO1/BCD.v
Z50 FC:/FPGA/VERILOG/EXO1/BCD.v
L0 34
R23
r1
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Z51 !s108 1311790755.751000
Z52 !s107 C:/FPGA/VERILOG/EXO1/BCD.v|
Z53 !s90 -reportprogress|300|-work|work|-vopt|-nocovercells|C:/FPGA/VERILOG/EXO1/BCD.v|
R25
R26
Z54 !s100 e7;0k6:zAc9ca]O9IUVf:0
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vhex_to_seg
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R19
R48
R49
R50
L0 3
R23
r1
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R51
R52
R53
R25
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vhorloge
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Z59 VoSUb[a3RcL0[=1oP_4BLV2
R19
Z60 w1311281910
Z61 8C:/FPGA/VERILOG/EXO1/tempo.v
Z62 FC:/FPGA/VERILOG/EXO1/tempo.v
L0 1
R23
r1
31
Z63 !s108 1311281927.831000
Z64 !s107 C:/FPGA/VERILOG/EXO1/tempo.v|
Z65 !s90 -reportprogress|300|-work|work|-vopt|-nocovercells|C:/FPGA/VERILOG/EXO1/tempo.v|
R25
R26
Z66 !s100 0R>nUN4VU>fLSCN8egU[B2
!s85 0
vmanip
Z67 IOIa:2a;cKONGbbC1O7Z0Q1
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R19
R60
R61
R62
L0 37
R23
r1
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R63
R64
R65
R25
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!s85 0
vreal_time_clk
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Z71 VXGJTZ=NCFL0hQT_9WTRR72
R19
R38
R39
R40
L0 2
R23
r1
31
R42
R43
R44
R25
R26
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vreal_time_clk_verilog
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R19
Z75 w1311792125
R39
R40
L0 2
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r1
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R44
R25
R26
R43
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vsync_reset_counter
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R19
Z80 w1311284452
Z81 8C:/FPGA/VERILOG/EXO1/01.v
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L0 1
R23
r1
31
Z83 !s108 1311284469.191000
Z84 !s107 C:/FPGA/VERILOG/EXO1/01.v|
Z85 !s90 -reportprogress|300|-work|work|-vopt|-nocovercells|C:/FPGA/VERILOG/EXO1/01.v|
R25
R26
Z86 !s100 oFZP0^RfS;cX<XZzhlWY@0
!s85 0
vtb_src
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R19
R80
R81
R82
L0 39
R23
r1
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R83
R84
R85
R25
R26
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!s85 0
vtest
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Z91 Vk<3<[f=78GX=_HO53D;7>3
R19
Z92 w1311273864
Z93 8C:/FPGA/VERILOG/EXO1/code.v
Z94 FC:/FPGA/VERILOG/EXO1/code.v
L0 20
R23
r1
31
R25
R26
Z95 !s108 1311273867.581000
Z96 !s107 C:/FPGA/VERILOG/EXO1/code.v|
Z97 !s90 -reportprogress|300|-work|work|-vopt|-nocovercells|C:/FPGA/VERILOG/EXO1/code.v|
Z98 !s100 K:0X^^@P[WdhN<=1_J@;81
!s85 0
vtimeunit
Z99 IeRmUV9`<mJZ`a>gL1U62c1
Z100 V[8Q2OQh2LlfoIbPZ0ki0K2
R19
Z101 w1311271746
R30
R31
L0 5
R23
r1
31
R33
R32
R25
R26
Z102 !s108 1311271959.378000
Z103 !s100 P7AcY_JOM4[[0R7;KBKLN0
!s85 0