"pmos" is a three-terminal PFET representation. The bulk node is
initially set to "vdd!" but is modifiable from the property list. If you
want a four-terminal PFET, use "pmos4".

This version netlists to a bidirectional device (rtranif0) when
simulated in Verilog. It has also been modified to have 0.1 units of
delay when simulated using Verilog.
