library verilog;
use verilog.vl_types.all;
entity two_bit_counter is
    port(
        \IN\            : in     vl_logic;
        \OUT\           : out    vl_logic;
        CLK             : in     vl_logic;
        RST             : in     vl_logic;
        ENABLE          : in     vl_logic
    );
end two_bit_counter;