`timescale 1ns / 1ns

module hex_to_seg(
input wire[3:0] hex,
input wire dp,
output reg[7:0] seg );

	always @*

	begin
	 case (hex)
	4'h0: seg[6:0] = 7'b0000001;
	4'h1: seg[6:0] = 7'b1001111;
	4'h2: seg[6:0] = 7'b0010010;
	4'h3: seg[6:0] = 7'b0000110;
	4'h4: seg[6:0] = 7'b1001100;
	4'h5: seg[6:0] = 7'b0100100;
	4'h6: seg[6:0] = 7'b0100000;
	4'h7: seg[6:0] = 7'b0001111;
	4'h8: seg[6:0] = 7'b0000000 ;
	4'h9: seg[6:0] = 7'b0000100 ;
	4'ha: seg[6:0] = 7'b0001000;
	4'hb: seg[6:0] = 7'b1100000;
	4'hc: seg[6:0] = 7'b0110001;
	4'hd: seg[6:0] = 7'b1000010;
	4'he: seg[6:0] = 7'b0110000;
	default : seg[6:0] = 7'b0111000; //4 'hf
	endcase

	seg[7] = dp;
	end
endmodule	

module hex_test
  (
  input wire clk,
  input wire[7:0] sw,
  output wire[3:0] an,
  output wire[7:0] seg );

   wire[7:0] inc;
   wire[7:0] led0, led1, led2 ,led3;
   
   assign inc = sw + 1; 
   

endmodule
/*
module BCDecode(BCDinpt, segcntrl);
  input [3:0] BCDinpt;
  output reg[6:0] segcntrl;
  
always @(BCDinpt);
  begin
    case(BCDinpt)
      0: segcntrl = 7'b1111110;
    /*  1: segcntrl = 7'b0110000;
      2: segcntrl = 7'b1101101;
      3: segcntrl = 7'b1111001;
      4: segcntrl = 7'b0110011;
      5: segcntrl = 7'b1011011;
      6: segcntrl = 7'b1011111;
      7: segcntrl = 7'b1110000;
      8: segcntrl = 7'b1111111;
      9: segcntrl = 7'b1111011;*/
/*      default: segcntrl = 7'b0000001;
    endcase
endmodule

/*
module test_BCD;
  reg [3:0] BCDin;
  wire [6:0] segout;
  
  BCDecode BCDmodule (BCDin, segout);
  initial //Clock generator
    begin
      BCDin = 4'b0000;
      BCDin = 4'b0001;
      BCDin = 4'b0010;
      BCDin = 4'b0011;
      BCDin = 4'b0100;
      BCDin = 4'b0101;
      BCDin = 4'b0110;
      BCDin = 4'b0111;
      BCDin = 4'b1000;
      BCDin = 4'b1001;
    end
    
  initial //Test Stimulus
    begin
      
    end

  initial
  $monitor ($stime, ,BCDin, , segout);
endmodule*/