library verilog;
use verilog.vl_types.all;
entity horloge is
    generic(
        period          : integer := 50000;
        N               : integer := 15;
        half            : vl_notype
    );
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        clkout          : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of period : constant is 1;
    attribute mti_svvh_generic_type of N : constant is 1;
    attribute mti_svvh_generic_type of half : constant is 3;
end horloge;