library verilog;
use verilog.vl_types.all;
entity hex_test is
    port(
        clk             : in     vl_logic;
        sw              : in     vl_logic_vector(7 downto 0);
        an              : out    vl_logic_vector(3 downto 0);
        seg             : out    vl_logic_vector(7 downto 0)
    );
end hex_test;