library verilog;
use verilog.vl_types.all;
entity real_time_clk_verilog is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        hour1           : out    vl_logic_vector(6 downto 0);
        hour2           : out    vl_logic_vector(6 downto 0);
        minute1         : out    vl_logic_vector(6 downto 0);
        minute2         : out    vl_logic_vector(6 downto 0);
        second1         : out    vl_logic_vector(6 downto 0);
        second2         : out    vl_logic_vector(6 downto 0);
        hr_A2           : in     vl_logic;
        min_A1          : in     vl_logic;
        sec_A0          : in     vl_logic;
        load            : in     vl_logic;
        data_in         : in     vl_logic_vector(7 downto 0)
    );
end real_time_clk_verilog;