library verilog;
use verilog.vl_types.all;
entity slow_clock is
    generic(
        MSB             : integer := 24
    );
    port(
        real_clk        : in     vl_logic;
        slow_clk        : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of MSB : constant is 1;
end slow_clock;