library verilog;
use verilog.vl_types.all;
entity shifter is
    port(
        result          : out    vl_logic_vector(7 downto 0);
        value_in        : in     vl_logic_vector(7 downto 0);
        direction       : in     vl_logic;
        \type\          : in     vl_logic_vector(1 downto 0);
        length          : in     vl_logic_vector(2 downto 0)
    );
end shifter;
