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# Created by Genus(TM) Synthesis Solution 16.10-p006_1 on Fri Dec 16 11:45:08 +0100 2016

# This file contains the RC script for /designs/digital_control_top

######################################################################

::legacy::set_attribute -quiet information_level 6 /
::legacy::set_attribute -quiet init_lib_search_path {. $LIB_DIR/tsl18fs520hdpm/lib/liberty/} /
::legacy::set_attribute -quiet common_ui false /
::legacy::set_attribute -quiet design_mode_process 230.0 /
::legacy::set_attribute -quiet phys_assume_met_fill 0.0 /
::legacy::set_attribute -quiet runtime_by_stage { {to_generic 1 26 1 11}  {first_condense 4 36 4 18}  {second_condense 2 39 2 21}  {reify 5 44 4 26}  {global_incr_map 3 47 2 29}  {incr_opt 4 54 4 34} } /
::legacy::set_attribute -quiet iopt_ultra_optimization true /
::legacy::set_attribute -quiet hdl_array_naming_style %s_%d_ /
::legacy::set_attribute -quiet partition_based_synthesis false /
::legacy::set_attribute -quiet tinfo_tstamp_file .rs_ffxj4w.tstamp /
::legacy::set_attribute -quiet max_cpus_per_server 0 /
::legacy::set_attribute -quiet script_search_path {. <path>} /
::legacy::set_attribute -quiet ultra_global_mapping true /
::legacy::set_attribute -quiet gen_module_prefix CDN_DP_ /
::legacy::set_attribute -quiet use_area_from_lef true /
::legacy::set_attribute -quiet leakage_power_effort medium /
::legacy::set_attribute -quiet remove_assigns true /
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_1ms/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_1s/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_2ms/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_2us/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_4ms/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_4us/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_8ms/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_8us/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_16ms/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_16us/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_32ms/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_32us/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_64ms/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_64us/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_128ms/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_128us/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_256ms/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_256us/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_512ms/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_512us/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_comb/drc_bufs4052/pins_in/I
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_i2c/instances_comb/g65/pins_in/S
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_i2c/instances_comb/g67/pins_in/I
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_io_control/instances_comb/g270/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_comb/g8081/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_comb/g8082/pins_in/A
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_comb/g8082/pins_in/B2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_comb/g8084/pins_in/A
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_comb/g8084/pins_in/B2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_comb/g8084/pins_in/C2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_comb/g8085/pins_in/A
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_comb/g8085/pins_in/B2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_comb/g8086/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_comb/g8087/pins_in/A1
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_comb/g8087/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_comb/g8088/pins_in/A1
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_scan_mux/instances_comb/g26/pins_in/S
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_scan_mux/instances_hier/wr_otp_cgc/instances_comb/g15/pins_in/A1
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_scan_mux/instances_comb/drc_bufs/pins_in/I
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_scan_mux/instances_comb/g209/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_scan_mux/instances_comb/g212/pins_in/A1
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_scan_mux/instances_comb/drc_bufs223/pins_in/I
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_scan_mux/instances_comb/drc_bufs227/pins_in/I
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_scan_wrapper/instances_comb/g204/pins_in/I
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_scan_wrapper/instances_comb/g205/pins_in/I
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_scan_wrapper/instances_comb/g529/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_scan_wrapper/instances_comb/g530/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_scan_wrapper/instances_comb/g532/pins_in/A1
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_scan_wrapper/instances_comb/g534/pins_in/A1
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_scan_wrapper/instances_comb/g536/pins_in/A1
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_scan_wrapper/instances_comb/g537/pins_in/A1
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1582/pins_in/C2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1583/pins_in/A
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1583/pins_in/C2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1584/pins_in/A1
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1584/pins_in/A3
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1585/pins_in/A1
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1586/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1586/pins_in/B2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1587/pins_in/B
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1587/pins_in/C1
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1587/pins_in/C2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1588/pins_in/A
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1588/pins_in/B
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1588/pins_in/C1
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1589/pins_in/A1
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1589/pins_in/A3
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1589/pins_in/A4
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1590/pins_in/B1
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1590/pins_in/B2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1590/pins_in/C1
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1590/pins_in/C2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1591/pins_in/A1
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1591/pins_in/A3
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1592/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1592/pins_in/A3
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1592/pins_in/A4
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1595/pins_in/A
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1595/pins_in/C1
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1595/pins_in/C2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1596/pins_in/A1
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1596/pins_in/A3
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1596/pins_in/A4
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1617/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1619/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1620/pins_in/A3
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1622/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1622/pins_in/A3
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1623/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1624/pins_in/A1
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1624/pins_in/A2
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1626/pins_in/A1
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1627/pins_in/A1
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1628/pins_in/I
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1629/pins_in/I
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1630/pins_in/I
::legacy::set_attribute -quiet break_timing_paths true /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1631/pins_in/I
::legacy::set_attribute -quiet phys_use_segment_parasitics true /
::legacy::set_attribute -quiet probabilistic_extraction true /
::legacy::set_attribute -quiet ple_correlation_factors {1.9000 2.0000} /
::legacy::set_attribute -quiet maximum_interval_of_vias inf /
::legacy::set_attribute -quiet ple_mode global /
::legacy::set_attribute -quiet operating_conditions ss_2p7v_125c /
::legacy::set_attribute -quiet tree_type balanced_tree /libraries/tsl18fs520hdpm_ss_2p7v_125c/operating_conditions/ss_2p7v_125c
::legacy::set_attribute -quiet tree_type balanced_tree /libraries/tsl18fs520hdpm_ss_2p7v_125c/operating_conditions/_nominal_
# BEGIN MSV SECTION
# END MSV SECTION
define_clock -name clk -domain domain_1 -period 1000000.0 -divide_period 1 -rise 0 -divide_rise 1 -fall 1 -divide_fall 2 -design /designs/digital_control_top /designs/digital_control_top/ports_in/clk_1M
define_clock -name scl -domain domain_1 -period 1000000.0 -divide_period 1 -rise 0 -divide_rise 1 -fall 1 -divide_fall 2 -design /designs/digital_control_top /designs/digital_control_top/ports_in/scl_in
define_clock -name sync_clk -domain domain_1 -period 1000000.0 -divide_period 1 -rise 0 -divide_rise 1 -fall 1 -divide_fall 2 -design /designs/digital_control_top /designs/digital_control_top/ports_in/sync_in
define_cost_group -design /designs/digital_control_top -name C2C
define_cost_group -design /designs/digital_control_top -name C2O
define_cost_group -design /designs/digital_control_top -name I2C
define_cost_group -design /designs/digital_control_top -name I2O
define_cost_group -design /designs/digital_control_top -name clk
define_cost_group -design /designs/digital_control_top -name scl
define_cost_group -design /designs/digital_control_top -name sync_clk
external_delay -accumulate -input {0.0 no_value 0.0 no_value} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name create_clock_delay_domain_1_clk_R_0 /designs/digital_control_top/ports_in/clk_1M
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/create_clock_delay_domain_1_clk_R_0
external_delay -accumulate -input {no_value 0.0 no_value 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -edge_fall -name create_clock_delay_domain_1_clk_F_0 /designs/digital_control_top/ports_in/clk_1M
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/create_clock_delay_domain_1_clk_F_0
external_delay -accumulate -input {0.0 no_value 0.0 no_value} -clock /designs/digital_control_top/timing/clock_domains/domain_1/scl -name create_clock_delay_domain_1_scl_R_0 /designs/digital_control_top/ports_in/scl_in
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/create_clock_delay_domain_1_scl_R_0
external_delay -accumulate -input {no_value 0.0 no_value 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/scl -edge_fall -name create_clock_delay_domain_1_scl_F_0 /designs/digital_control_top/ports_in/scl_in
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/create_clock_delay_domain_1_scl_F_0
external_delay -accumulate -input {0.0 no_value 0.0 no_value} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -name create_clock_delay_domain_1_sync_clk_R_0 /designs/digital_control_top/ports_in/sync_in
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/create_clock_delay_domain_1_sync_clk_R_0
external_delay -accumulate -input {no_value 0.0 no_value 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name create_clock_delay_domain_1_sync_clk_F_0 /designs/digital_control_top/ports_in/sync_in
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/create_clock_delay_domain_1_sync_clk_F_0
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -edge_fall -name clk_gating_check_1 /designs/digital_control_top/instances_hier/i_dig_scan_mux/instances_comb/drc_bufs227/pins_in/I
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_1
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_1
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_2 /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_2us/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_2
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_2
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_22 /designs/digital_control_top/instances_hier/i_dig_scan_mux/instances_hier/wr_otp_cgc/instances_comb/g15/pins_in/A1
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_22
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_22
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -edge_fall -name clk_gating_check_23 /designs/digital_control_top/instances_hier/i_dig_scan_mux/instances_comb/g212/pins_in/A1
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_23
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_23
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -edge_fall -name clk_gating_check_24 /designs/digital_control_top/instances_hier/i_dig_scan_mux/instances_comb/drc_bufs223/pins_in/I
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_24
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_24
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_25 {/designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1619/pins_in/A2 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1622/pins_in/A2 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1631/pins_in/I}
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_25
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_25
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -edge_fall -name clk_gating_check_26 {/designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1627/pins_in/A1 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1622/pins_in/A3 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1626/pins_in/A1 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1620/pins_in/A3 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1624/pins_in/A2}
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_26
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_26
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -edge_fall -name clk_gating_check_27 {/designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1624/pins_in/A1 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1617/pins_in/A2 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1623/pins_in/A2 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1628/pins_in/I}
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_27
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_27
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -edge_fall -name clk_gating_check_28 {/designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1586/pins_in/B2 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1586/pins_in/A2 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1583/pins_in/A}
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_28
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_28
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -edge_fall -name clk_gating_check_29 {/designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1591/pins_in/A3 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1589/pins_in/A4 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1583/pins_in/C2 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1584/pins_in/A1 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1630/pins_in/I}
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_29
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_29
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -edge_fall -name clk_gating_check_30 {/designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1584/pins_in/A3 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1629/pins_in/I}
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_30
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_30
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -name clk_gating_check_31 /designs/digital_control_top/instances_hier/i_dig_io_control/instances_comb/g270/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_31
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_31
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/scl -name clk_gating_check_32 /designs/digital_control_top/instances_hier/i_dig_io_control/instances_comb/g270/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_32
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_32
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_33 /designs/digital_control_top/instances_hier/i_dig_io_control/instances_comb/g270/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_33
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_33
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_34 /designs/digital_control_top/instances_hier/i_dig_scan_wrapper/instances_comb/g537/pins_in/A1
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_34
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_34
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/scl -name clk_gating_check_35 /designs/digital_control_top/instances_hier/i_dig_scan_wrapper/instances_comb/g537/pins_in/A1
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_35
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_35
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_36 /designs/digital_control_top/instances_hier/i_dig_scan_wrapper/instances_comb/g537/pins_in/A1
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_36
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_36
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -name clk_gating_check_37 /designs/digital_control_top/instances_hier/i_dig_scan_mux/instances_comb/g209/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_37
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_37
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/scl -name clk_gating_check_38 /designs/digital_control_top/instances_hier/i_dig_scan_mux/instances_comb/g209/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_38
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_38
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_39 /designs/digital_control_top/instances_hier/i_dig_scan_mux/instances_comb/g209/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_39
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_39
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -name clk_gating_check_40 /designs/digital_control_top/instances_hier/i_dig_scan_mux/instances_comb/g26/pins_in/S
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_40
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_40
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/scl -name clk_gating_check_41 /designs/digital_control_top/instances_hier/i_dig_scan_mux/instances_comb/g26/pins_in/S
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_41
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_41
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_42 /designs/digital_control_top/instances_hier/i_dig_scan_mux/instances_comb/g26/pins_in/S
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_42
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_42
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/scl -edge_fall -name clk_gating_check_43 /designs/digital_control_top/instances_hier/i_dig_scan_mux/instances_comb/drc_bufs/pins_in/I
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_43
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_43
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/scl -name clk_gating_check_44 /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_comb/drc_bufs4052/pins_in/I
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_44
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_44
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/scl -edge_fall -name clk_gating_check_45 /designs/digital_control_top/instances_hier/i_dig_i2c/instances_comb/g67/pins_in/I
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_45
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_45
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/scl -edge_fall -name clk_gating_check_46 /designs/digital_control_top/instances_hier/i_dig_i2c/instances_comb/g65/pins_in/S
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_46
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_46
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/scl -name clk_gating_check_47 {/designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1619/pins_in/A2 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1622/pins_in/A2 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1631/pins_in/I}
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_47
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_47
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/scl -name clk_gating_check_48 {/designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1627/pins_in/A1 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1622/pins_in/A3 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1626/pins_in/A1 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1620/pins_in/A3 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1624/pins_in/A2}
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_48
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_48
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/scl -name clk_gating_check_49 {/designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1624/pins_in/A1 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1617/pins_in/A2 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1623/pins_in/A2 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1628/pins_in/I}
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_49
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_49
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/scl -name clk_gating_check_50 {/designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1586/pins_in/B2 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1586/pins_in/A2 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1585/pins_in/A1}
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_50
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_50
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/scl -name clk_gating_check_51 {/designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1591/pins_in/A3 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1589/pins_in/A4 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1584/pins_in/A1 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1630/pins_in/I}
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_51
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_51
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/scl -edge_fall -name clk_gating_check_52 {/designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1584/pins_in/A3 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1629/pins_in/I}
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_52
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_52
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_53 /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_comb/g8088/pins_in/A1
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_53
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_53
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -name clk_gating_check_54 /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_comb/g8086/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_54
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_54
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_55 /designs/digital_control_top/instances_hier/i_dig_scan_wrapper/instances_comb/g205/pins_in/I
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_55
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_55
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_56 /designs/digital_control_top/instances_hier/i_dig_scan_wrapper/instances_comb/g204/pins_in/I
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_56
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_56
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_57 /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_comb/g8085/pins_in/B2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_57
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_57
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -name clk_gating_check_58 /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_comb/g8085/pins_in/A
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_58
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_58
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -name clk_gating_check_59 /designs/digital_control_top/instances_hier/i_dig_scan_wrapper/instances_comb/g532/pins_in/A1
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_59
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_59
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -name clk_gating_check_62 /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_comb/g8084/pins_in/C2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_62
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_62
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_63 /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_comb/g8084/pins_in/B2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_63
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_63
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -name clk_gating_check_65 /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_comb/g8084/pins_in/A
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_65
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_65
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_66 /designs/digital_control_top/instances_hier/i_dig_scan_wrapper/instances_comb/g534/pins_in/A1
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_66
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_66
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_67 {/designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1619/pins_in/A2 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1622/pins_in/A2 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1631/pins_in/I}
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_67
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_67
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_68 {/designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1627/pins_in/A1 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1622/pins_in/A3 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1626/pins_in/A1 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1620/pins_in/A3 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1624/pins_in/A2}
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_68
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_68
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_69 {/designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1624/pins_in/A1 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1617/pins_in/A2 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1623/pins_in/A2 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1628/pins_in/I}
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_69
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_69
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_70 {/designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1586/pins_in/B2 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1586/pins_in/A2}
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_70
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_70
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -name clk_gating_check_71 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1630/pins_in/I
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_71
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_71
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_72 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1629/pins_in/I
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_72
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_72
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_74 /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_comb/g8082/pins_in/A
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_74
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_74
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_75 /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_comb/g8087/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_75
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_75
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -name clk_gating_check_76 /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_comb/g8082/pins_in/B2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_76
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_76
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_77 /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_comb/g8087/pins_in/A1
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_77
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_77
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_78 /designs/digital_control_top/instances_hier/i_dig_scan_wrapper/instances_comb/g536/pins_in/A1
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_78
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_78
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_79 /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_512us/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_79
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_79
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_80 /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_512ms/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_80
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_80
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_81 /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_256us/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_81
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_81
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_82 /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_256ms/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_82
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_82
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_83 /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_128us/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_83
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_83
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_84 /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_128ms/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_84
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_84
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_85 /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_64us/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_85
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_85
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_86 /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_64ms/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_86
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_86
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_87 /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_32us/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_87
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_87
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_88 /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_32ms/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_88
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_88
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_89 /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_16us/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_89
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_89
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_90 /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_16ms/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_90
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_90
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_91 /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_8us/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_91
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_91
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_92 /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_8ms/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_92
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_92
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_93 /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_4us/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_93
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_93
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_94 /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_4ms/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_94
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_94
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_95 /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_2ms/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_95
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_95
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_96 /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_1s/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_96
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_96
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_97 /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_1ms/instances_comb/g17/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_97
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_97
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -edge_fall -name clk_gating_check_98 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1592/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_98
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_98
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -edge_fall -name clk_gating_check_99 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1592/pins_in/A3
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_99
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_99
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -edge_fall -name clk_gating_check_100 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1592/pins_in/A4
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_100
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_100
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -name clk_gating_check_101 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1585/pins_in/A1
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_101
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_101
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/scl -edge_fall -name clk_gating_check_102 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1587/pins_in/B
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_102
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_102
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/scl -edge_fall -name clk_gating_check_103 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1587/pins_in/C1
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_103
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_103
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/scl -edge_fall -name clk_gating_check_104 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1587/pins_in/C2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_104
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_104
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/scl -name clk_gating_check_105 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1583/pins_in/A
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_105
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_105
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/scl -name clk_gating_check_106 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1583/pins_in/C2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_106
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_106
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/scl -edge_fall -name clk_gating_check_107 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1582/pins_in/C2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_107
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_107
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_108 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1582/pins_in/C2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_108
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_108
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_109 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1595/pins_in/A
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_109
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_109
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_110 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1595/pins_in/C1
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_110
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_110
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_111 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1595/pins_in/C2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_111
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_111
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_112 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1590/pins_in/B1
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_112
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_112
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_113 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1590/pins_in/B2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_113
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_113
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_114 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1590/pins_in/C1
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_114
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_114
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_115 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1590/pins_in/C2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_115
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_115
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -name clk_gating_check_116 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1584/pins_in/A1
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_116
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_116
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -name clk_gating_check_117 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1584/pins_in/A3
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_117
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_117
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_118 /designs/digital_control_top/instances_hier/i_dig_scan_wrapper/instances_comb/g530/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_118
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_118
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_119 /designs/digital_control_top/instances_hier/i_dig_scan_wrapper/instances_comb/g529/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_119
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_119
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -name clk_gating_check_120 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1596/pins_in/A1
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_120
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_120
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -name clk_gating_check_121 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1596/pins_in/A3
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_121
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_121
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -name clk_gating_check_122 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1596/pins_in/A4
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_122
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_122
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_123 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1591/pins_in/A1
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_123
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_123
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_124 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1591/pins_in/A3
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_124
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_124
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_125 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1583/pins_in/A
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_125
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_125
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_126 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1583/pins_in/C2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_126
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_126
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_127 /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_comb/g8081/pins_in/A2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_127
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_127
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_128 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1589/pins_in/A1
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_128
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_128
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_129 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1589/pins_in/A3
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_129
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_129
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -edge_fall -name clk_gating_check_130 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1589/pins_in/A4
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_130
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_130
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk -name clk_gating_check_131 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1585/pins_in/A1
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_131
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_131
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/clk -edge_fall -name clk_gating_check_132 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1582/pins_in/C2
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_132
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_132
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/scl -name clk_gating_check_133 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1588/pins_in/A
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_133
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_133
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/scl -name clk_gating_check_134 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1588/pins_in/B
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_134
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_134
external_delay -accumulate -output {no_value no_value 0.0 0.0} -clock /designs/digital_control_top/timing/clock_domains/domain_1/scl -name clk_gating_check_135 /designs/digital_control_top/instances_hier/i_dig_test_mux/instances_comb/g1588/pins_in/C1
::legacy::set_attribute -quiet clock_network_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_135
::legacy::set_attribute -quiet clock_source_latency_included true /designs/digital_control_top/timing/external_delays/clk_gating_check_135
path_group -paths [specify_paths -to /designs/digital_control_top/timing/clock_domains/domain_1/clk]  -name clk -group /designs/digital_control_top/timing/cost_groups/clk -user_priority -1047552
path_group -paths [specify_paths -to /designs/digital_control_top/timing/clock_domains/domain_1/scl]  -name scl -group /designs/digital_control_top/timing/cost_groups/scl -user_priority -1047552
path_group -paths [specify_paths -to /designs/digital_control_top/timing/clock_domains/domain_1/sync_clk]  -name sync_clk -group /designs/digital_control_top/timing/cost_groups/sync_clk -user_priority -1047552
path_disable -paths [specify_paths -lenient -from /designs/digital_control_top/timing/clock_domains/domain_1/scl -to /designs/digital_control_top/timing/clock_domains/domain_1/clk]  -name digital_control_top._line_29 -user_priority -887808
::legacy::set_attribute -quiet sdc_filename_linenumber {{../../constraints/digital_control_top.rc.sdc 29}} /designs/digital_control_top/timing/exceptions/path_disables/digital_control_top._line_29
path_disable -paths [specify_paths -lenient -from /designs/digital_control_top/timing/clock_domains/domain_1/clk -to /designs/digital_control_top/timing/clock_domains/domain_1/scl]  -name digital_control_top._line_30 -user_priority -887808
::legacy::set_attribute -quiet sdc_filename_linenumber {{../../constraints/digital_control_top.rc.sdc 30}} /designs/digital_control_top/timing/exceptions/path_disables/digital_control_top._line_30
path_disable -paths [specify_paths -lenient -from /designs/digital_control_top/ports_in/sync_in -to {/designs/digital_control_top/timing/clock_domains/domain_1/clk /designs/digital_control_top/timing/clock_domains/domain_1/scl}]  -name zipped_path_disable_0 -user_priority -902144
::legacy::set_attribute -quiet sdc_filename_linenumber {{../../constraints/digital_control_top.rc.sdc 36} {../../constraints/digital_control_top.rc.sdc 33}} /designs/digital_control_top/timing/exceptions/path_disables/zipped_path_disable_0
path_disable -paths [specify_paths -lenient -from {/designs/digital_control_top/timing/clock_domains/domain_1/clk /designs/digital_control_top/timing/clock_domains/domain_1/scl} -to /designs/digital_control_top/ports_in/sync_in]  -name zipped_path_disable_1 -user_priority -894976
::legacy::set_attribute -quiet sdc_filename_linenumber {{../../constraints/digital_control_top.rc.sdc 35} {../../constraints/digital_control_top.rc.sdc 32}} /designs/digital_control_top/timing/exceptions/path_disables/zipped_path_disable_1
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/designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/EmitReg_reg_0_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/SelectEmitReg_reg_0_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/SelectEmitReg_reg_1_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_7_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_6_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_6_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_5_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_5_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_4_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_4_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_3_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_3_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/WR_reg /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_2_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_2_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_1_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_1_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_0_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_0_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/start_detect/instances_seq/q_int_reg /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/stop_detect/instances_seq/q_int_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/cpt_otp_reg_0_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/cpt_otp_reg_1_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/cpt_otp_reg_2_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/cpt_otp_reg_3_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_cnt_reg_0_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_cnt_reg_1_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_cnt_reg_2_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_cnt_reg_3_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_0_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_1_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_2_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_3_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_4_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_5_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_6_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_7_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/i2c_prog_reg_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/i2c_prog_sync_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/i2c_read_reg_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/i2c_read_sync_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_cmd_clr_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_en_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_loaded_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_por_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_prog_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_read_dly_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_read_done_dly_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_read_done_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_read_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/state_reg_0_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/state_reg_1_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/state_reg_2_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/state_reg_3_ /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_4us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_64ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_32us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_512us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_256ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_128ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_1ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_2ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_8ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_4ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_16ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_256us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_1s/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_8us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_512ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_64us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_32ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_16us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_128us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/cp_bulk_fw_fsm_reg /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/cp_bulk_rev_fsm_reg /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/cp_ovlo_prot_fsm_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_2us/instances_seq/gate_reg} -to {/designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/start_detect/instances_seq/temp_int_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/ovlo_sync_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/vout_ovp_sync_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/vout_sc_sync_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/uvlo_sync_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/vout_sc_reg_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/vout_ovp_reg_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/ovlo_reg_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/uvlo_reg_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/ovlo_latch_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/uvlo_latch_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/tsd_sync_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/vout_sc_latch_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/vout_ovp_latch_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/tsd_reg_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/uvlo_sync2_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/vout_ovp_sync2_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/vout_sc_sync2_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/ovlo_sync2_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vout_ocp/instances_seq/deb_out_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vout_ocp/instances_seq/cntr_reg_2_ /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vout_ocp/instances_seq/cntr_reg_1_ /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vout_ocp/instances_seq/cntr_reg_0_ /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vin_rng/instances_seq/cntr_reg_0_ /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vin_rng/instances_seq/cntr_reg_1_ /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vin_rng/instances_seq/cntr_reg_2_ /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vin_rng/instances_seq/deb_out_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vin_ocp/instances_seq/deb_out_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vin_ocp/instances_seq/cntr_reg_3_ /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vin_ocp/instances_seq/cntr_reg_1_ /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vin_ocp/instances_seq/cntr_reg_2_ /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vin_ocp/instances_seq/cntr_reg_0_ /designs/digital_control_top/instances_hier/i_dig_scan_mux/instances_hier/wr_otp_cgc/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_seq/clk_2us_50_50_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_seq/clk_1s_50_50_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_seq/clk_256us_50_50_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_seq/clk_512ms_50_50_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_seq/clk_256ms_50_50_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_seq/clk_512us_50_50_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_seq/clk_2ms_50_50_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_seq/clk_2s_50_50_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_seq/clk_64ms_50_50_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_seq/clk_1ms_50_50_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_seq/clk_16us_50_50_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_seq/clk_4us_50_50_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_seq/clk_8ms_50_50_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_seq/clk_8us_50_50_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_seq/clk_16ms_50_50_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_seq/clk_4ms_50_50_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_seq/clk_32ms_50_50_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_seq/clk_32us_50_50_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_seq/clk_64us_50_50_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_seq/clk_128ms_50_50_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_seq/clk_128us_50_50_reg /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/otp_reg_reg_2_ /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/otp_reg_reg_1_ /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/otp_reg_reg_0_ /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/otp_reg_reg_3_ /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/otp_reg_reg_6_ /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/otp_reg_reg_5_ /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/otp_reg_reg_4_ /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/otp_reg_reg_7_ /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/tb_vout_sc_msk_reg /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/tb_en_reg_reg /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/tb_spare4_reg /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/tb_stop_in_idle_reg /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/tb_tsd_msk_reg /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/tb_uvlo_msk_reg /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/tb_vout_ovp_msk_reg /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/cursen_reg_0_ /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/digmux_sel_reg_5_ /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/prog_reg /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/cursen_reg_1_ /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/digmux_sel_reg_0_ /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/re_latch_reg /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/tb_byp_vin_in_range_reg /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/otp_emul_zero_reg /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/tb_spare3_reg /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/tb_force_phi1_reg /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/tb_force_phi2_reg /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/tb_force_sync0_reg /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/digmux_sel_reg_1_ /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/digmux_sel_reg_2_ /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/tb_force_sync1_reg /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/tb_io_speed_mode_reg /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/tb_ocp_msk_reg /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/tb_osc_alt_freq_reg /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/digmux_sel_reg_3_ /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/tb_ovlo_msk_reg /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/tb_spare1_reg /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/digmux_sel_reg_4_ /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/tb_spare2_reg /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/tb_en_reg_sel_reg /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/tb_test_state_reg /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/amux_sel_reg_1_ /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/amux_sel_reg_2_ /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/amux_sel_reg_0_ /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/amux_sel_reg_3_ /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/scan_mode_reg /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/sync_pullup_states_reg /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/valid_comps_reg /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/en_iprech_reg /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/cp_fsm_exit_reg /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/active_states_reg /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/cp_ok_out_states_reg /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/state_timer_cnt_reg_4_ /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/state_timer_cnt_reg_3_ /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/state_timer_cnt_reg_2_ /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/state_timer_cnt_reg_1_ /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/state_timer_cnt_reg_0_ /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/cfly_pre_750us_reg /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/tile_detected_reg /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/master_detected_reg /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/state_reg_10_ /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/state_reg_0_ /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/state_reg_3_ /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/state_reg_2_ /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/state_reg_1_ /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/state_reg_6_ /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/state_reg_9_ /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/state_reg_8_ /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/state_reg_7_ /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/state_reg_5_ /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/state_reg_12_ /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/state_reg_11_ /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/state_reg_4_ /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_hier/I_deb_prot_pulse/instances_seq/cntr_reg_3_ /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_hier/I_deb_prot_pulse/instances_seq/cntr_reg_2_ /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_hier/I_deb_prot_pulse/instances_seq/cntr_reg_1_ /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_hier/I_deb_prot_pulse/instances_seq/cntr_reg_0_ /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_hier/I_deb_prot_pulse/instances_seq/deb_out_reg /designs/digital_control_top/instances_hier/i_dig_io_control/instances_hier/dig_deb_sync_in/instances_seq/deb_out_reg /designs/digital_control_top/instances_hier/i_dig_io_control/instances_hier/dig_deb_sync_in/instances_seq/cntr_reg_2_ /designs/digital_control_top/instances_hier/i_dig_io_control/instances_hier/dig_deb_sync_in/instances_seq/cntr_reg_0_ /designs/digital_control_top/instances_hier/i_dig_io_control/instances_hier/dig_deb_sync_in/instances_seq/cntr_reg_1_ /designs/digital_control_top/instances_hier/i_dig_io_control/instances_hier/dig_deb_en_in/instances_seq/deb_out_reg /designs/digital_control_top/instances_hier/i_dig_io_control/instances_hier/dig_deb_en_in/instances_seq/cntr_reg_3_ /designs/digital_control_top/instances_hier/i_dig_io_control/instances_hier/dig_deb_en_in/instances_seq/cntr_reg_1_ /designs/digital_control_top/instances_hier/i_dig_io_control/instances_hier/dig_deb_en_in/instances_seq/cntr_reg_2_ /designs/digital_control_top/instances_hier/i_dig_io_control/instances_hier/dig_deb_en_in/instances_seq/cntr_reg_0_ /designs/digital_control_top/instances_hier/i_dig_io_control/instances_seq/cp_ok_inb_latch_reg /designs/digital_control_top/instances_hier/i_dig_io_control/instances_seq/cp_ok_inb_sync2_reg /designs/digital_control_top/instances_hier/i_dig_io_control/instances_seq/cp_ok_in_sync_reg /designs/digital_control_top/instances_hier/i_dig_io_control/instances_seq/cp_ok_inb_sync_reg /designs/digital_control_top/instances_hier/i_dig_io_control/instances_seq/sync_pin_sync_reg /designs/digital_control_top/instances_hier/i_dig_io_control/instances_seq/cp_ok_in_reg_reg /designs/digital_control_top/instances_hier/i_dig_io_control/instances_seq/cp_ok_inb_reg_reg /designs/digital_control_top/instances_hier/i_dig_io_control/instances_seq/sync_pin_reg_reg /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/stop_detect/instances_seq/temp_int_reg /designs/digital_control_top/instances_seq/test_mode_reg_reg /designs/digital_control_top/instances_seq/test_mode_tmp_reg /designs/digital_control_top/instances_hier/I_dig_otp_lock/instances_seq/otp_prog_lock_reg /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/CptBit_reg_0_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/CptBit_reg_1_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/CptBit_reg_2_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/CptBit_reg_3_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/CurrentState_reg_0_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/CurrentState_reg_1_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/CurrentState_reg_2_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/CurrentState_reg_3_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/CurrentState_reg_4_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/CurrentState_reg_5_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/addr_bus_reg_0_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/addr_bus_reg_1_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/addr_bus_reg_2_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/addr_bus_reg_3_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/addr_bus_reg_4_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/addr_bus_reg_5_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/addr_bus_reg_6_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/addr_bus_reg_7_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/write_bus_reg_0_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/write_bus_reg_1_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/write_bus_reg_2_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/write_bus_reg_3_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/write_bus_reg_4_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/write_bus_reg_5_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/write_bus_reg_6_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/write_bus_reg_7_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/EmitReg_reg_7_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/EmitReg_reg_6_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/EmitReg_reg_5_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/EmitReg_reg_4_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/EmitReg_reg_3_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/EmitReg_reg_2_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/EmitReg_reg_1_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/EmitReg_reg_0_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/SelectEmitReg_reg_0_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/SelectEmitReg_reg_1_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_7_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_6_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_6_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_5_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_5_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_4_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_4_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_3_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_3_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/WR_reg /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_2_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_2_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_1_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_1_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_0_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_0_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/start_detect/instances_seq/q_int_reg /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/stop_detect/instances_seq/q_int_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/cpt_otp_reg_0_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/cpt_otp_reg_1_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/cpt_otp_reg_2_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/cpt_otp_reg_3_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_cnt_reg_0_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_cnt_reg_1_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_cnt_reg_2_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_cnt_reg_3_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_0_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_1_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_2_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_3_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_4_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_5_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_6_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_7_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/i2c_prog_reg_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/i2c_prog_sync_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/i2c_read_reg_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/i2c_read_sync_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_cmd_clr_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_en_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_loaded_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_por_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_prog_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_read_dly_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_read_done_dly_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_read_done_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_read_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/state_reg_0_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/state_reg_1_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/state_reg_2_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/state_reg_3_ /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_4us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_64ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_32us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_512us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_256ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_128ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_1ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_2ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_8ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_4ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_16ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_256us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_1s/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_8us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_512ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_64us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_32ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_16us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_128us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/cp_bulk_fw_fsm_reg /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/cp_bulk_rev_fsm_reg /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/cp_ovlo_prot_fsm_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_2us/instances_seq/gate_reg}]  -name C2C -group /designs/digital_control_top/timing/cost_groups/C2C
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/designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/write_bus_reg_7_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/EmitReg_reg_7_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/EmitReg_reg_6_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/EmitReg_reg_5_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/EmitReg_reg_4_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/EmitReg_reg_3_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/EmitReg_reg_2_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/EmitReg_reg_1_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/EmitReg_reg_0_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/SelectEmitReg_reg_0_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/SelectEmitReg_reg_1_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_7_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_6_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_6_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_5_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_5_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_4_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_4_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_3_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_3_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/WR_reg /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_2_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_2_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_1_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_1_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_0_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_0_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/start_detect/instances_seq/q_int_reg /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/stop_detect/instances_seq/q_int_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/cpt_otp_reg_0_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/cpt_otp_reg_1_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/cpt_otp_reg_2_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/cpt_otp_reg_3_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_cnt_reg_0_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_cnt_reg_1_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_cnt_reg_2_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_cnt_reg_3_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_0_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_1_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_2_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_3_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_4_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_5_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_6_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_7_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/i2c_prog_reg_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/i2c_prog_sync_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/i2c_read_reg_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/i2c_read_sync_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_cmd_clr_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_en_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_loaded_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_por_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_prog_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_read_dly_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_read_done_dly_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_read_done_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_read_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/state_reg_0_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/state_reg_1_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/state_reg_2_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/state_reg_3_ /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_4us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_64ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_32us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_512us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_256ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_128ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_1ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_2ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_8ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_4ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_16ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_256us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_1s/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_8us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_512ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_64us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_32ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_16us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_128us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/cp_bulk_fw_fsm_reg /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/cp_bulk_rev_fsm_reg /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/cp_ovlo_prot_fsm_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_2us/instances_seq/gate_reg} -to {/designs/digital_control_top/ports_out/en_uvlo_cmp /designs/digital_control_top/ports_out/en_osc /designs/digital_control_top/ports_out/en_vref /designs/digital_control_top/ports_out/en_iref /designs/digital_control_top/ports_out/en_tsd /designs/digital_control_top/ports_out/en_ovlo_cmp /designs/digital_control_top/ports_out/en_out /designs/digital_control_top/ports_out/en_en_in /designs/digital_control_top/ports_out/en_en_out /designs/digital_control_top/ports_out/sync_out /designs/digital_control_top/ports_out/en_sync_in /designs/digital_control_top/ports_out/en_sync_out /designs/digital_control_top/ports_out/en_sync_pullup /designs/digital_control_top/ports_out/cp_ok_out /designs/digital_control_top/ports_out/en_cp_ok_in /designs/digital_control_top/ports_out/en_cp_ok_out /designs/digital_control_top/ports_out/en_cp_pwr /designs/digital_control_top/ports_out/cp_clk_phi1 /designs/digital_control_top/ports_out/cp_clk_phi2 /designs/digital_control_top/ports_out/cp_bulk_rev /designs/digital_control_top/ports_out/cp_bulk_fw /designs/digital_control_top/ports_out/cp_bulk_prech /designs/digital_control_top/ports_out/cp_ovlo_prot /designs/digital_control_top/ports_out/cp_ovlo_prot_pulse /designs/digital_control_top/ports_out/en_iprech /designs/digital_control_top/ports_out/en_vin_rng_cmp /designs/digital_control_top/ports_out/en_ocp_cmp /designs/digital_control_top/ports_out/en_vout_sc_cmp /designs/digital_control_top/ports_out/en_vout_ovp_cmp /designs/digital_control_top/ports_out/cfly_pre_750us {/designs/digital_control_top/ports_out/otp_din[7]} {/designs/digital_control_top/ports_out/otp_din[6]} {/designs/digital_control_top/ports_out/otp_din[5]} {/designs/digital_control_top/ports_out/otp_din[4]} {/designs/digital_control_top/ports_out/otp_din[3]} {/designs/digital_control_top/ports_out/otp_din[2]} {/designs/digital_control_top/ports_out/otp_din[1]} {/designs/digital_control_top/ports_out/otp_din[0]} /designs/digital_control_top/ports_out/otp_en /designs/digital_control_top/ports_out/otp_por /designs/digital_control_top/ports_out/otp_prog /designs/digital_control_top/ports_out/otp_read /designs/digital_control_top/ports_out/otp_cur0 /designs/digital_control_top/ports_out/otp_cur1 {/designs/digital_control_top/ports_out/otp_osc[2]} {/designs/digital_control_top/ports_out/otp_osc[1]} {/designs/digital_control_top/ports_out/otp_osc[0]} {/designs/digital_control_top/ports_out/otp_vref[6]} {/designs/digital_control_top/ports_out/otp_vref[5]} {/designs/digital_control_top/ports_out/otp_vref[4]} {/designs/digital_control_top/ports_out/otp_vref[3]} /designs/digital_control_top/ports_out/sda_out /designs/digital_control_top/ports_out/test_mode_ic /designs/digital_control_top/ports_out/io_testmode /designs/digital_control_top/ports_out/tb_osc_alt_freq /designs/digital_control_top/ports_out/tb_spare1 /designs/digital_control_top/ports_out/tb_spare2 /designs/digital_control_top/ports_out/dmux_out /designs/digital_control_top/ports_out/en_dmux_out {/designs/digital_control_top/ports_out/amux_sel[15]} {/designs/digital_control_top/ports_out/amux_sel[14]} {/designs/digital_control_top/ports_out/amux_sel[13]} {/designs/digital_control_top/ports_out/amux_sel[12]} {/designs/digital_control_top/ports_out/amux_sel[11]} {/designs/digital_control_top/ports_out/amux_sel[10]} {/designs/digital_control_top/ports_out/amux_sel[9]} {/designs/digital_control_top/ports_out/amux_sel[8]} {/designs/digital_control_top/ports_out/amux_sel[7]} {/designs/digital_control_top/ports_out/amux_sel[6]} {/designs/digital_control_top/ports_out/amux_sel[5]} {/designs/digital_control_top/ports_out/amux_sel[4]} {/designs/digital_control_top/ports_out/amux_sel[3]} {/designs/digital_control_top/ports_out/amux_sel[2]} {/designs/digital_control_top/ports_out/amux_sel[1]} /designs/digital_control_top/ports_out/scan_mode_out}]  -name C2O -group /designs/digital_control_top/timing/cost_groups/C2O
path_group -paths [specify_paths -from {/designs/digital_control_top/ports_in/porb /designs/digital_control_top/ports_in/uvlo /designs/digital_control_top/ports_in/clk_1M /designs/digital_control_top/ports_in/vcore_on_vout /designs/digital_control_top/ports_in/vref_ok /designs/digital_control_top/ports_in/ovlo /designs/digital_control_top/ports_in/tsd /designs/digital_control_top/ports_in/en_in /designs/digital_control_top/ports_in/sync_in /designs/digital_control_top/ports_in/cp_ok_in /designs/digital_control_top/ports_in/cp_nov_phi1 /designs/digital_control_top/ports_in/cp_nov_phi2 /designs/digital_control_top/ports_in/vin_ocp /designs/digital_control_top/ports_in/vin_above_range /designs/digital_control_top/ports_in/vin_below_range /designs/digital_control_top/ports_in/vout_ocp /designs/digital_control_top/ports_in/vout_sc /designs/digital_control_top/ports_in/vout_ovp /designs/digital_control_top/ports_in/metal_option {/designs/digital_control_top/ports_in/otp_bits[7]} {/designs/digital_control_top/ports_in/otp_bits[6]} {/designs/digital_control_top/ports_in/otp_bits[5]} {/designs/digital_control_top/ports_in/otp_bits[4]} {/designs/digital_control_top/ports_in/otp_bits[3]} {/designs/digital_control_top/ports_in/otp_bits[2]} {/designs/digital_control_top/ports_in/otp_bits[1]} {/designs/digital_control_top/ports_in/otp_bits[0]} /designs/digital_control_top/ports_in/sda_in /designs/digital_control_top/ports_in/scl_in {/designs/digital_control_top/ports_in/rev_id[3]} {/designs/digital_control_top/ports_in/rev_id[2]} {/designs/digital_control_top/ports_in/rev_id[1]} {/designs/digital_control_top/ports_in/rev_id[0]} /designs/digital_control_top/ports_in/test_speed_up /designs/digital_control_top/ports_in/spare_in_tst0 /designs/digital_control_top/ports_in/spare_in_tst1 /designs/digital_control_top/ports_in/spare_in_tst2 /designs/digital_control_top/ports_in/scan_mode /designs/digital_control_top/ports_in/scan_in /designs/digital_control_top/ports_in/scan_clk /designs/digital_control_top/ports_in/scan_en /designs/digital_control_top/ports_in/scan_rstb} -to {/designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/start_detect/instances_seq/temp_int_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/ovlo_sync_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/vout_ovp_sync_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/vout_sc_sync_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/uvlo_sync_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/vout_sc_reg_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/vout_ovp_reg_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/ovlo_reg_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/uvlo_reg_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/ovlo_latch_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/uvlo_latch_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/tsd_sync_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/vout_sc_latch_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/vout_ovp_latch_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/tsd_reg_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/uvlo_sync2_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/vout_ovp_sync2_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/vout_sc_sync2_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_seq/ovlo_sync2_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vout_ocp/instances_seq/deb_out_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vout_ocp/instances_seq/cntr_reg_2_ /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vout_ocp/instances_seq/cntr_reg_1_ /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vout_ocp/instances_seq/cntr_reg_0_ /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vin_rng/instances_seq/cntr_reg_0_ /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vin_rng/instances_seq/cntr_reg_1_ /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vin_rng/instances_seq/cntr_reg_2_ /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vin_rng/instances_seq/deb_out_reg /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vin_ocp/instances_seq/deb_out_reg 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/designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/write_bus_reg_6_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/write_bus_reg_7_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/EmitReg_reg_7_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/EmitReg_reg_6_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/EmitReg_reg_5_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/EmitReg_reg_4_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/EmitReg_reg_3_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/EmitReg_reg_2_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/EmitReg_reg_1_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/EmitReg_reg_0_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/SelectEmitReg_reg_0_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/SelectEmitReg_reg_1_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_7_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_6_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_6_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_5_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_5_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_4_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_4_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_3_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_3_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/WR_reg /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_2_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_2_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_1_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_1_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/Synch_ReceivedRegister_reg_0_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/instances_seq/ReceivedRegister_reg_0_ /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/start_detect/instances_seq/q_int_reg /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/stop_detect/instances_seq/q_int_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/cpt_otp_reg_0_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/cpt_otp_reg_1_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/cpt_otp_reg_2_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/cpt_otp_reg_3_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_cnt_reg_0_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_cnt_reg_1_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_cnt_reg_2_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_cnt_reg_3_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_0_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_1_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_2_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_3_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_4_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_5_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_6_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/data_mask_reg_7_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/i2c_prog_reg_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/i2c_prog_sync_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/i2c_read_reg_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/i2c_read_sync_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_cmd_clr_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_en_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_loaded_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_por_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_prog_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_read_dly_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_read_done_dly_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_read_done_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/otp_read_reg /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/state_reg_0_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/state_reg_1_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/state_reg_2_ /designs/digital_control_top/instances_hier/I_dig_otp/instances_seq/state_reg_3_ /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_4us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_64ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_32us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_512us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_256ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_128ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_1ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_2ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_8ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_4ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_16ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_256us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_1s/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_8us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_512ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_64us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_32ms/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_16us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_128us/instances_seq/gate_reg /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/cp_bulk_fw_fsm_reg /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/cp_bulk_rev_fsm_reg /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_seq/cp_ovlo_prot_fsm_reg /designs/digital_control_top/instances_hier/i_dig_clk/instances_hier/cgc_clk_2us/instances_seq/gate_reg}]  -name I2C -group /designs/digital_control_top/timing/cost_groups/I2C
path_group -paths [specify_paths -from {/designs/digital_control_top/ports_in/porb /designs/digital_control_top/ports_in/uvlo /designs/digital_control_top/ports_in/clk_1M /designs/digital_control_top/ports_in/vcore_on_vout /designs/digital_control_top/ports_in/vref_ok /designs/digital_control_top/ports_in/ovlo /designs/digital_control_top/ports_in/tsd /designs/digital_control_top/ports_in/en_in /designs/digital_control_top/ports_in/sync_in /designs/digital_control_top/ports_in/cp_ok_in /designs/digital_control_top/ports_in/cp_nov_phi1 /designs/digital_control_top/ports_in/cp_nov_phi2 /designs/digital_control_top/ports_in/vin_ocp /designs/digital_control_top/ports_in/vin_above_range /designs/digital_control_top/ports_in/vin_below_range /designs/digital_control_top/ports_in/vout_ocp /designs/digital_control_top/ports_in/vout_sc /designs/digital_control_top/ports_in/vout_ovp /designs/digital_control_top/ports_in/metal_option {/designs/digital_control_top/ports_in/otp_bits[7]} {/designs/digital_control_top/ports_in/otp_bits[6]} {/designs/digital_control_top/ports_in/otp_bits[5]} {/designs/digital_control_top/ports_in/otp_bits[4]} {/designs/digital_control_top/ports_in/otp_bits[3]} {/designs/digital_control_top/ports_in/otp_bits[2]} {/designs/digital_control_top/ports_in/otp_bits[1]} {/designs/digital_control_top/ports_in/otp_bits[0]} /designs/digital_control_top/ports_in/sda_in /designs/digital_control_top/ports_in/scl_in {/designs/digital_control_top/ports_in/rev_id[3]} {/designs/digital_control_top/ports_in/rev_id[2]} {/designs/digital_control_top/ports_in/rev_id[1]} {/designs/digital_control_top/ports_in/rev_id[0]} /designs/digital_control_top/ports_in/test_speed_up /designs/digital_control_top/ports_in/spare_in_tst0 /designs/digital_control_top/ports_in/spare_in_tst1 /designs/digital_control_top/ports_in/spare_in_tst2 /designs/digital_control_top/ports_in/scan_mode /designs/digital_control_top/ports_in/scan_in /designs/digital_control_top/ports_in/scan_clk /designs/digital_control_top/ports_in/scan_en /designs/digital_control_top/ports_in/scan_rstb} -to {/designs/digital_control_top/ports_out/en_uvlo_cmp /designs/digital_control_top/ports_out/en_osc /designs/digital_control_top/ports_out/en_vref /designs/digital_control_top/ports_out/en_iref /designs/digital_control_top/ports_out/en_tsd /designs/digital_control_top/ports_out/en_ovlo_cmp /designs/digital_control_top/ports_out/en_out /designs/digital_control_top/ports_out/en_en_in /designs/digital_control_top/ports_out/en_en_out /designs/digital_control_top/ports_out/sync_out /designs/digital_control_top/ports_out/en_sync_in /designs/digital_control_top/ports_out/en_sync_out /designs/digital_control_top/ports_out/en_sync_pullup /designs/digital_control_top/ports_out/cp_ok_out /designs/digital_control_top/ports_out/en_cp_ok_in /designs/digital_control_top/ports_out/en_cp_ok_out /designs/digital_control_top/ports_out/en_cp_pwr /designs/digital_control_top/ports_out/cp_clk_phi1 /designs/digital_control_top/ports_out/cp_clk_phi2 /designs/digital_control_top/ports_out/cp_bulk_rev /designs/digital_control_top/ports_out/cp_bulk_fw /designs/digital_control_top/ports_out/cp_bulk_prech /designs/digital_control_top/ports_out/cp_ovlo_prot /designs/digital_control_top/ports_out/cp_ovlo_prot_pulse /designs/digital_control_top/ports_out/en_iprech /designs/digital_control_top/ports_out/en_vin_rng_cmp /designs/digital_control_top/ports_out/en_ocp_cmp /designs/digital_control_top/ports_out/en_vout_sc_cmp /designs/digital_control_top/ports_out/en_vout_ovp_cmp /designs/digital_control_top/ports_out/cfly_pre_750us {/designs/digital_control_top/ports_out/otp_din[7]} {/designs/digital_control_top/ports_out/otp_din[6]} {/designs/digital_control_top/ports_out/otp_din[5]} {/designs/digital_control_top/ports_out/otp_din[4]} {/designs/digital_control_top/ports_out/otp_din[3]} {/designs/digital_control_top/ports_out/otp_din[2]} {/designs/digital_control_top/ports_out/otp_din[1]} {/designs/digital_control_top/ports_out/otp_din[0]} /designs/digital_control_top/ports_out/otp_en /designs/digital_control_top/ports_out/otp_por /designs/digital_control_top/ports_out/otp_prog /designs/digital_control_top/ports_out/otp_read /designs/digital_control_top/ports_out/otp_cur0 /designs/digital_control_top/ports_out/otp_cur1 {/designs/digital_control_top/ports_out/otp_osc[2]} {/designs/digital_control_top/ports_out/otp_osc[1]} {/designs/digital_control_top/ports_out/otp_osc[0]} {/designs/digital_control_top/ports_out/otp_vref[6]} {/designs/digital_control_top/ports_out/otp_vref[5]} {/designs/digital_control_top/ports_out/otp_vref[4]} {/designs/digital_control_top/ports_out/otp_vref[3]} /designs/digital_control_top/ports_out/sda_out /designs/digital_control_top/ports_out/test_mode_ic /designs/digital_control_top/ports_out/io_testmode /designs/digital_control_top/ports_out/tb_osc_alt_freq /designs/digital_control_top/ports_out/tb_spare1 /designs/digital_control_top/ports_out/tb_spare2 /designs/digital_control_top/ports_out/dmux_out /designs/digital_control_top/ports_out/en_dmux_out {/designs/digital_control_top/ports_out/amux_sel[15]} {/designs/digital_control_top/ports_out/amux_sel[14]} {/designs/digital_control_top/ports_out/amux_sel[13]} {/designs/digital_control_top/ports_out/amux_sel[12]} {/designs/digital_control_top/ports_out/amux_sel[11]} {/designs/digital_control_top/ports_out/amux_sel[10]} {/designs/digital_control_top/ports_out/amux_sel[9]} {/designs/digital_control_top/ports_out/amux_sel[8]} {/designs/digital_control_top/ports_out/amux_sel[7]} {/designs/digital_control_top/ports_out/amux_sel[6]} {/designs/digital_control_top/ports_out/amux_sel[5]} {/designs/digital_control_top/ports_out/amux_sel[4]} {/designs/digital_control_top/ports_out/amux_sel[3]} {/designs/digital_control_top/ports_out/amux_sel[2]} {/designs/digital_control_top/ports_out/amux_sel[1]} /designs/digital_control_top/ports_out/scan_mode_out}]  -name I2O -group /designs/digital_control_top/timing/cost_groups/I2O
# BEGIN DFT SECTION
::legacy::set_attribute -quiet dft_scan_style muxed_scan /
::legacy::set_attribute -quiet dft_scanbit_waveform_analysis false /
::legacy::set_attribute -quiet dft_dont_scan true /designs/digital_control_top/instances_hier/i_dig_regs/instances_seq/scan_mode_reg
define_dft test_clock -name scan_clk -domain scan_clk -period 50000.0 -divide_period 1 -rise 1 -divide_rise 2 -fall 9 -divide_fall 10 -controllable /designs/digital_control_top/ports_in/scan_clk
define_test_signal -name test_scan_enable -active high   /designs/digital_control_top/ports_in/scan_en -function shift_enable  -index 0   -no_ideal  
::legacy::set_attribute -quiet default_shift_enable true /designs/digital_control_top/dft/test_signals/test_scan_enable
::legacy::set_attribute -quiet dedicated_pin true /designs/digital_control_top/dft/test_signals/test_scan_enable
::legacy::set_attribute -quiet lec_value auto /designs/digital_control_top/dft/test_signals/test_scan_enable
::legacy::set_attribute -quiet atpg_use none /designs/digital_control_top/dft/test_signals/test_scan_enable
define_test_signal -name test_scan_mode -active high   /designs/digital_control_top/ports_in/scan_mode -function test_mode  -index 0   -no_ideal -skip_has_fanout_check 
::legacy::set_attribute -quiet dedicated_pin true /designs/digital_control_top/dft/test_signals/test_scan_mode
::legacy::set_attribute -quiet has_fanout true /designs/digital_control_top/dft/test_signals/test_scan_mode
::legacy::set_attribute -quiet lec_value auto /designs/digital_control_top/dft/test_signals/test_scan_mode
::legacy::set_attribute -quiet atpg_use none /designs/digital_control_top/dft/test_signals/test_scan_mode
define_test_signal -name scan_rstb -active high   /designs/digital_control_top/ports_in/scan_rstb -function async_set_reset  -index 0   -no_ideal -skip_has_fanout_check 
::legacy::set_attribute -quiet user_defined_signal false /designs/digital_control_top/dft/test_signals/scan_rstb
::legacy::set_attribute -quiet dedicated_pin true /designs/digital_control_top/dft/test_signals/scan_rstb
::legacy::set_attribute -quiet lec_value auto /designs/digital_control_top/dft/test_signals/scan_rstb
::legacy::set_attribute -quiet atpg_use none /designs/digital_control_top/dft/test_signals/scan_rstb
::legacy::set_attribute -quiet atpg_use none /designs/digital_control_top/dft/test_clock_domains/scan_clk/scan_clk
define_dft formal_verification_constraint -name wdl_cons_0 -pin /designs/digital_control_top/ports_in/scan_en  -golden low   -tool_derived -redefine /designs/digital_control_top
define_dft formal_verification_constraint -name wdl_cons_1 -pin /designs/digital_control_top/ports_in/scan_en    -revised low -tool_derived -redefine /designs/digital_control_top
define_dft scan_chain -name DFT_chain_1 -shift_enable /designs/digital_control_top/dft/test_signals/test_scan_enable   -sdi /designs/digital_control_top/ports_in/scan_in -sdo /designs/digital_control_top/instances_hier/i_dig_scan_mux/pins_in/scan_out      -non_shared_out 
define_dft scan_chain -name DFT_chain_1 -sdi /designs/digital_control_top/ports_in/scan_in  -sdo /designs/digital_control_top/instances_hier/i_dig_scan_mux/pins_in/scan_out  -analyze -non_shared_out    -write_script_flow
# END DFT SECTION
::legacy::set_attribute -quiet dft_test_signals_snapshot {test_scan_enable test_scan_mode scan_rstb } /designs/digital_control_top
::legacy::set_attribute -quiet max_transition 2000.0 /designs/digital_control_top
::legacy::set_attribute -quiet max_capacitance 500.0 /designs/digital_control_top
::legacy::set_attribute -quiet qos_by_stage {{to_generic {wns -11111111} {tns -111111111} {vep -111111111} {area 94440} {cell_count 2233} {utilization  0.00} {runtime 1 26 1 11} }{first_condense {wns -11111111} {tns -111111111} {vep -111111111} {area 81103} {cell_count 1958} {utilization  0.00} {runtime 4 36 4 18} }{second_condense {wns -11111111} {tns -111111111} {vep -111111111} {area 80790} {cell_count 1940} {utilization  0.00} {runtime 2 39 2 21} }{reify {wns 475216} {tns 0} {vep 0} {area 72990} {cell_count 1411} {utilization  0.00} {runtime 5 44 4 26} }{global_incr_map {wns 474770} {tns 0} {vep 0} {area 74200} {cell_count 1413} {utilization  0.00} {runtime 3 47 2 29} }{incr_opt {wns 214748365} {tns 0} {vep 0} {area 72805} {cell_count 1325} {utilization  0.00} {runtime 4 54 4 34} }} /designs/digital_control_top
::legacy::set_attribute -quiet hdl_user_name digital_control_top /designs/digital_control_top
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_cgc.v} {$BLOCK_PATH/rtl_v}} {default -v2001 {SYNTHESIS} {../../rtl_v/digital_control_top.v} {$BLOCK_PATH/rtl_v}} {default -v2001 {SYNTHESIS} {../../rtl_v/dig_clk.v} {$BLOCK_PATH/rtl_v}} {default -v2001 {SYNTHESIS} {../../rtl_v/dig_scan_mux.v} {$BLOCK_PATH/rtl_v}} {default -v2001 {SYNTHESIS} {../../rtl_v/dig_main_fsm.v} {$BLOCK_PATH/rtl_v}} {default -v2001 {SYNTHESIS} {../../rtl_v/dig_comps.v} {$BLOCK_PATH/rtl_v}} {default -v2001 {SYNTHESIS} {../../rtl_v/dig_io_control.v} {$BLOCK_PATH/rtl_v}} {default -v2001 {SYNTHESIS} {../../rtl_v/dig_otp.v} {$BLOCK_PATH/rtl_v}} {default -v2001 {SYNTHESIS} {../../rtl_v/dig_deb.v} {$BLOCK_PATH/rtl_v}} {default -v2001 {SYNTHESIS} {../../rtl_v/dig_deb_pos.v} {$BLOCK_PATH/rtl_v}} {default -v2001 {SYNTHESIS} {../../rtl_v/dig_i2c_fsm.v} {$BLOCK_PATH/rtl_v}} {default -v2001 {SYNTHESIS} {../../rtl_v/dig_i2c.v} {$BLOCK_PATH/rtl_v}} {default -v2001 {SYNTHESIS} {../../rtl_v/dig_i2c_vedge.v} {$BLOCK_PATH/rtl_v}} {default -v2001 {SYNTHESIS} {../../rtl_v/dig_scan_wrapper.v} {$BLOCK_PATH/rtl_v}} {default -v2001 {SYNTHESIS} {../../rtl_v/dig_test_mux.v} {$BLOCK_PATH/rtl_v}} {default -v2001 {SYNTHESIS} {../../rtl_v/dig_otp_lock.v} {$BLOCK_PATH/rtl_v}} {default -v2001 {SYNTHESIS} {../../rtl_v/dig_regs.v} {$BLOCK_PATH/rtl_v}} {default -v2001 {SYNTHESIS} {../../rtl_v/dig_decode4to16.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top
::legacy::set_attribute -quiet verification_directory fv/digital_control_top /designs/digital_control_top
::legacy::set_attribute -quiet seq_reason_deleted {{i_dig_clk/cgc_clk_2s/gate_reg unloaded} {i_dig_i2c/I_dig_i2c_fsm/RD_reg unloaded} {i_dig_i2c/I_dig_i2c_fsm/high_speed_reg unloaded} {I_dig_otp/state_reg_5_ {{merged with I_dig_otp/otp_en_reg}}} {I_dig_otp/state_reg_4_ {{merged with I_dig_otp/otp_prog_reg}}} {i_dig_main_fsm/en_cp_pwr_fsm_reg {{merged with i_dig_main_fsm/cp_bulk_fw_fsm_reg}}}} /designs/digital_control_top
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/porb
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/uvlo
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/clk_1M
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/vcore_on_vout
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/vref_ok
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/ovlo
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/tsd
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/en_in
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/sync_in
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/cp_ok_in
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/cp_nov_phi1
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/cp_nov_phi2
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/vin_ocp
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/vin_above_range
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/vin_below_range
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/vout_ocp
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/vout_sc
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/vout_ovp
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/metal_option
::legacy::set_attribute -quiet min_transition no_value {/designs/digital_control_top/ports_in/otp_bits[7]}
::legacy::set_attribute -quiet min_transition no_value {/designs/digital_control_top/ports_in/otp_bits[6]}
::legacy::set_attribute -quiet min_transition no_value {/designs/digital_control_top/ports_in/otp_bits[5]}
::legacy::set_attribute -quiet min_transition no_value {/designs/digital_control_top/ports_in/otp_bits[4]}
::legacy::set_attribute -quiet min_transition no_value {/designs/digital_control_top/ports_in/otp_bits[3]}
::legacy::set_attribute -quiet min_transition no_value {/designs/digital_control_top/ports_in/otp_bits[2]}
::legacy::set_attribute -quiet min_transition no_value {/designs/digital_control_top/ports_in/otp_bits[1]}
::legacy::set_attribute -quiet min_transition no_value {/designs/digital_control_top/ports_in/otp_bits[0]}
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/sda_in
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/scl_in
::legacy::set_attribute -quiet min_transition no_value {/designs/digital_control_top/ports_in/rev_id[3]}
::legacy::set_attribute -quiet min_transition no_value {/designs/digital_control_top/ports_in/rev_id[2]}
::legacy::set_attribute -quiet min_transition no_value {/designs/digital_control_top/ports_in/rev_id[1]}
::legacy::set_attribute -quiet min_transition no_value {/designs/digital_control_top/ports_in/rev_id[0]}
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/test_speed_up
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/spare_in_tst0
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/spare_in_tst1
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/spare_in_tst2
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/scan_mode
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/scan_in
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/scan_clk
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/scan_en
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_in/scan_rstb
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/en_uvlo_cmp
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/en_uvlo_cmp
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/en_uvlo_cmp
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/en_uvlo_cmp
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/en_uvlo_cmp
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/en_osc
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/en_osc
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/en_osc
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/en_osc
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/en_osc
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/en_vref
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/en_vref
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/en_vref
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/en_vref
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/en_vref
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/en_iref
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/en_iref
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/en_iref
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/en_iref
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/en_iref
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/en_tsd
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/en_tsd
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/en_tsd
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/en_tsd
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/en_tsd
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/en_ovlo_cmp
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/en_ovlo_cmp
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/en_ovlo_cmp
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/en_ovlo_cmp
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/en_ovlo_cmp
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/en_out
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/en_out
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/en_out
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/en_out
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/en_out
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/en_en_in
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/en_en_in
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/en_en_in
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/en_en_in
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/en_en_in
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/en_en_out
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/en_en_out
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/en_en_out
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/en_en_out
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/en_en_out
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/sync_out
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/sync_out
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/sync_out
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/sync_out
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/sync_out
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/en_sync_in
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/en_sync_in
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/en_sync_in
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/en_sync_in
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/en_sync_in
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/en_sync_out
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/en_sync_out
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/en_sync_out
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/en_sync_out
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/en_sync_out
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/en_sync_pullup
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/en_sync_pullup
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/en_sync_pullup
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/en_sync_pullup
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/en_sync_pullup
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/cp_ok_out
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/cp_ok_out
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/cp_ok_out
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/cp_ok_out
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/cp_ok_out
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/en_cp_ok_in
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/en_cp_ok_in
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/en_cp_ok_in
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/en_cp_ok_in
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/en_cp_ok_in
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/en_cp_ok_out
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/en_cp_ok_out
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/en_cp_ok_out
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/en_cp_ok_out
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/en_cp_ok_out
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/en_cp_pwr
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/en_cp_pwr
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/en_cp_pwr
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/en_cp_pwr
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/en_cp_pwr
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/cp_clk_phi1
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/cp_clk_phi1
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/cp_clk_phi1
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/cp_clk_phi1
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/cp_clk_phi1
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/cp_clk_phi2
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/cp_clk_phi2
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/cp_clk_phi2
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/cp_clk_phi2
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/cp_clk_phi2
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/cp_bulk_rev
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/cp_bulk_rev
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/cp_bulk_rev
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/cp_bulk_rev
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/cp_bulk_rev
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/cp_bulk_fw
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/cp_bulk_fw
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/cp_bulk_fw
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/cp_bulk_fw
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/cp_bulk_fw
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/cp_bulk_prech
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/cp_bulk_prech
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/cp_bulk_prech
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/cp_bulk_prech
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/cp_bulk_prech
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/cp_ovlo_prot
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/cp_ovlo_prot
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/cp_ovlo_prot
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/cp_ovlo_prot
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/cp_ovlo_prot
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/cp_ovlo_prot_pulse
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/cp_ovlo_prot_pulse
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/cp_ovlo_prot_pulse
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/cp_ovlo_prot_pulse
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/cp_ovlo_prot_pulse
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/en_iprech
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/en_iprech
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/en_iprech
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/en_iprech
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/en_iprech
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/en_vin_rng_cmp
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/en_vin_rng_cmp
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/en_vin_rng_cmp
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/en_vin_rng_cmp
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/en_vin_rng_cmp
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/en_ocp_cmp
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::legacy::set_attribute -quiet min_transition no_value {/designs/digital_control_top/ports_out/amux_sel[11]}
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} {/designs/digital_control_top/ports_out/amux_sel[11]}
::legacy::set_attribute -quiet external_pin_cap_min 200.0 {/designs/digital_control_top/ports_out/amux_sel[10]}
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} {/designs/digital_control_top/ports_out/amux_sel[10]}
::legacy::set_attribute -quiet external_capacitance_min 200.0 {/designs/digital_control_top/ports_out/amux_sel[10]}
::legacy::set_attribute -quiet min_transition no_value {/designs/digital_control_top/ports_out/amux_sel[10]}
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} {/designs/digital_control_top/ports_out/amux_sel[10]}
::legacy::set_attribute -quiet external_pin_cap_min 200.0 {/designs/digital_control_top/ports_out/amux_sel[9]}
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} {/designs/digital_control_top/ports_out/amux_sel[9]}
::legacy::set_attribute -quiet external_capacitance_min 200.0 {/designs/digital_control_top/ports_out/amux_sel[9]}
::legacy::set_attribute -quiet min_transition no_value {/designs/digital_control_top/ports_out/amux_sel[9]}
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} {/designs/digital_control_top/ports_out/amux_sel[9]}
::legacy::set_attribute -quiet external_pin_cap_min 200.0 {/designs/digital_control_top/ports_out/amux_sel[8]}
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} {/designs/digital_control_top/ports_out/amux_sel[8]}
::legacy::set_attribute -quiet external_capacitance_min 200.0 {/designs/digital_control_top/ports_out/amux_sel[8]}
::legacy::set_attribute -quiet min_transition no_value {/designs/digital_control_top/ports_out/amux_sel[8]}
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} {/designs/digital_control_top/ports_out/amux_sel[8]}
::legacy::set_attribute -quiet external_pin_cap_min 200.0 {/designs/digital_control_top/ports_out/amux_sel[7]}
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} {/designs/digital_control_top/ports_out/amux_sel[7]}
::legacy::set_attribute -quiet external_capacitance_min 200.0 {/designs/digital_control_top/ports_out/amux_sel[7]}
::legacy::set_attribute -quiet min_transition no_value {/designs/digital_control_top/ports_out/amux_sel[7]}
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} {/designs/digital_control_top/ports_out/amux_sel[7]}
::legacy::set_attribute -quiet external_pin_cap_min 200.0 {/designs/digital_control_top/ports_out/amux_sel[6]}
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} {/designs/digital_control_top/ports_out/amux_sel[6]}
::legacy::set_attribute -quiet external_capacitance_min 200.0 {/designs/digital_control_top/ports_out/amux_sel[6]}
::legacy::set_attribute -quiet min_transition no_value {/designs/digital_control_top/ports_out/amux_sel[6]}
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} {/designs/digital_control_top/ports_out/amux_sel[6]}
::legacy::set_attribute -quiet external_pin_cap_min 200.0 {/designs/digital_control_top/ports_out/amux_sel[5]}
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} {/designs/digital_control_top/ports_out/amux_sel[5]}
::legacy::set_attribute -quiet external_capacitance_min 200.0 {/designs/digital_control_top/ports_out/amux_sel[5]}
::legacy::set_attribute -quiet min_transition no_value {/designs/digital_control_top/ports_out/amux_sel[5]}
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} {/designs/digital_control_top/ports_out/amux_sel[5]}
::legacy::set_attribute -quiet external_pin_cap_min 200.0 {/designs/digital_control_top/ports_out/amux_sel[4]}
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} {/designs/digital_control_top/ports_out/amux_sel[4]}
::legacy::set_attribute -quiet external_capacitance_min 200.0 {/designs/digital_control_top/ports_out/amux_sel[4]}
::legacy::set_attribute -quiet min_transition no_value {/designs/digital_control_top/ports_out/amux_sel[4]}
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} {/designs/digital_control_top/ports_out/amux_sel[4]}
::legacy::set_attribute -quiet external_pin_cap_min 200.0 {/designs/digital_control_top/ports_out/amux_sel[3]}
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} {/designs/digital_control_top/ports_out/amux_sel[3]}
::legacy::set_attribute -quiet external_capacitance_min 200.0 {/designs/digital_control_top/ports_out/amux_sel[3]}
::legacy::set_attribute -quiet min_transition no_value {/designs/digital_control_top/ports_out/amux_sel[3]}
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} {/designs/digital_control_top/ports_out/amux_sel[3]}
::legacy::set_attribute -quiet external_pin_cap_min 200.0 {/designs/digital_control_top/ports_out/amux_sel[2]}
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} {/designs/digital_control_top/ports_out/amux_sel[2]}
::legacy::set_attribute -quiet external_capacitance_min 200.0 {/designs/digital_control_top/ports_out/amux_sel[2]}
::legacy::set_attribute -quiet min_transition no_value {/designs/digital_control_top/ports_out/amux_sel[2]}
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} {/designs/digital_control_top/ports_out/amux_sel[2]}
::legacy::set_attribute -quiet external_pin_cap_min 200.0 {/designs/digital_control_top/ports_out/amux_sel[1]}
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} {/designs/digital_control_top/ports_out/amux_sel[1]}
::legacy::set_attribute -quiet external_capacitance_min 200.0 {/designs/digital_control_top/ports_out/amux_sel[1]}
::legacy::set_attribute -quiet min_transition no_value {/designs/digital_control_top/ports_out/amux_sel[1]}
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} {/designs/digital_control_top/ports_out/amux_sel[1]}
::legacy::set_attribute -quiet external_pin_cap_min 200.0 /designs/digital_control_top/ports_out/scan_mode_out
::legacy::set_attribute -quiet external_capacitance_max {200.0 200.0} /designs/digital_control_top/ports_out/scan_mode_out
::legacy::set_attribute -quiet external_capacitance_min 200.0 /designs/digital_control_top/ports_out/scan_mode_out
::legacy::set_attribute -quiet min_transition no_value /designs/digital_control_top/ports_out/scan_mode_out
::legacy::set_attribute -quiet external_pin_cap {200.0 200.0} /designs/digital_control_top/ports_out/scan_mode_out
::legacy::set_attribute -quiet hdl_user_name dig_otp /designs/digital_control_top/subdesigns/dig_otp
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_otp.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_otp
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_otp
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/I_dig_otp/subports_in/DFT_sdi
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/I_dig_otp/subports_in/DFT_sen
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/I_dig_otp/subports_out/DFT_sdo
::legacy::set_attribute -quiet hdl_user_name dig_otp_lock /designs/digital_control_top/subdesigns/dig_otp_lock
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_otp_lock.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_otp_lock
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_otp_lock
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/I_dig_otp_lock/subports_in/DFT_sdi
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/I_dig_otp_lock/subports_in/DFT_sen
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/I_dig_otp_lock/subports_out/DFT_sdo
::legacy::set_attribute -quiet hdl_user_name dig_clk /designs/digital_control_top/subdesigns/dig_clk
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_cgc.v} {$BLOCK_PATH/rtl_v}} {default -v2001 {SYNTHESIS} {../../rtl_v/dig_clk.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_clk
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_clk
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_clk/subports_in/DFT_sdi
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_clk/subports_out/DFT_sdo
::legacy::set_attribute -quiet hdl_user_name dig_cgc /designs/digital_control_top/subdesigns/dig_cgc_434
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_cgc.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_cgc_434
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_cgc_434
::legacy::set_attribute -quiet hdl_user_name dig_cgc /designs/digital_control_top/subdesigns/dig_cgc_424
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_cgc.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_cgc_424
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_cgc_424
::legacy::set_attribute -quiet hdl_user_name dig_cgc /designs/digital_control_top/subdesigns/dig_cgc_433
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_cgc.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_cgc_433
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_cgc_433
::legacy::set_attribute -quiet hdl_user_name dig_cgc /designs/digital_control_top/subdesigns/dig_cgc
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_cgc.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_cgc
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_cgc
::legacy::set_attribute -quiet hdl_user_name dig_cgc /designs/digital_control_top/subdesigns/dig_cgc_432
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_cgc.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_cgc_432
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_cgc_432
::legacy::set_attribute -quiet hdl_user_name dig_cgc /designs/digital_control_top/subdesigns/dig_cgc_442
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_cgc.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_cgc_442
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_cgc_442
::legacy::set_attribute -quiet hdl_user_name dig_cgc /designs/digital_control_top/subdesigns/dig_cgc_431
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_cgc.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_cgc_431
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_cgc_431
::legacy::set_attribute -quiet hdl_user_name dig_cgc /designs/digital_control_top/subdesigns/dig_cgc_441
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_cgc.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_cgc_441
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_cgc_441
::legacy::set_attribute -quiet hdl_user_name dig_cgc /designs/digital_control_top/subdesigns/dig_cgc_430
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_cgc.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_cgc_430
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_cgc_430
::legacy::set_attribute -quiet hdl_user_name dig_cgc /designs/digital_control_top/subdesigns/dig_cgc_440
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_cgc.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_cgc_440
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_cgc_440
::legacy::set_attribute -quiet hdl_user_name dig_cgc /designs/digital_control_top/subdesigns/dig_cgc_429
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_cgc.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_cgc_429
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_cgc_429
::legacy::set_attribute -quiet hdl_user_name dig_cgc /designs/digital_control_top/subdesigns/dig_cgc_439
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_cgc.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_cgc_439
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_cgc_439
::legacy::set_attribute -quiet hdl_user_name dig_cgc /designs/digital_control_top/subdesigns/dig_cgc_428
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_cgc.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_cgc_428
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_cgc_428
::legacy::set_attribute -quiet hdl_user_name dig_cgc /designs/digital_control_top/subdesigns/dig_cgc_438
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_cgc.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_cgc_438
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_cgc_438
::legacy::set_attribute -quiet hdl_user_name dig_cgc /designs/digital_control_top/subdesigns/dig_cgc_427
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_cgc.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_cgc_427
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_cgc_427
::legacy::set_attribute -quiet hdl_user_name dig_cgc /designs/digital_control_top/subdesigns/dig_cgc_437
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_cgc.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_cgc_437
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_cgc_437
::legacy::set_attribute -quiet hdl_user_name dig_cgc /designs/digital_control_top/subdesigns/dig_cgc_426
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_cgc.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_cgc_426
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_cgc_426
::legacy::set_attribute -quiet hdl_user_name dig_cgc /designs/digital_control_top/subdesigns/dig_cgc_436
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_cgc.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_cgc_436
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_cgc_436
::legacy::set_attribute -quiet hdl_user_name dig_cgc /designs/digital_control_top/subdesigns/dig_cgc_425
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_cgc.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_cgc_425
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_cgc_425
::legacy::set_attribute -quiet hdl_user_name dig_cgc /designs/digital_control_top/subdesigns/dig_cgc_435
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_cgc.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_cgc_435
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_cgc_435
::legacy::set_attribute -quiet hdl_user_name dig_comps /designs/digital_control_top/subdesigns/dig_comps
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_comps.v} {$BLOCK_PATH/rtl_v}} {default -v2001 {SYNTHESIS} {../../rtl_v/dig_deb.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_comps
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_comps
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_comps/subports_in/DFT_sdi
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_comps/subports_in/DFT_sen
::legacy::set_attribute -quiet hdl_user_name dig_deb /designs/digital_control_top/subdesigns/dig_deb_WIDTH4_RESET1h0
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_deb.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_deb_WIDTH4_RESET1h0
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_deb_WIDTH4_RESET1h0
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vin_ocp/subports_in/DFT_sdi
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vin_ocp/subports_in/DFT_sen
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vin_ocp/subports_out/DFT_sdo
::legacy::set_attribute -quiet preserve size_delete_ok /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vin_ocp/instances_comb/rm_assigns_buf_DFT_sdo
::legacy::set_attribute -quiet hdl_user_name dig_deb /designs/digital_control_top/subdesigns/dig_deb_WIDTH3_RESET1h0
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_deb.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_deb_WIDTH3_RESET1h0
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_deb_WIDTH3_RESET1h0
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vin_rng/subports_in/DFT_sdi
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vin_rng/subports_in/DFT_sen
::legacy::set_attribute -quiet hdl_user_name dig_deb /designs/digital_control_top/subdesigns/dig_deb_WIDTH3_RESET1h0_1
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_deb.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_deb_WIDTH3_RESET1h0_1
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_deb_WIDTH3_RESET1h0_1
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vout_ocp/subports_in/DFT_sdi
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_comps/instances_hier/I_dig_deb_vout_ocp/subports_in/DFT_sen
::legacy::set_attribute -quiet is_sop_cluster true /designs/digital_control_top/subdesigns/dig_decode4to16
::legacy::set_attribute -quiet hdl_user_name dig_decode4to16 /designs/digital_control_top/subdesigns/dig_decode4to16
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_decode4to16.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_decode4to16
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_decode4to16
::legacy::set_attribute -quiet hdl_user_name dig_i2c /designs/digital_control_top/subdesigns/dig_i2c
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_i2c_fsm.v} {$BLOCK_PATH/rtl_v}} {default -v2001 {SYNTHESIS} {../../rtl_v/dig_i2c.v} {$BLOCK_PATH/rtl_v}} {default -v2001 {SYNTHESIS} {../../rtl_v/dig_i2c_vedge.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_i2c
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_i2c
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_i2c/subports_in/DFT_sdi
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_i2c/subports_in/DFT_sen
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_i2c/subports_out/DFT_sdo
::legacy::set_attribute -quiet is_sop_cluster true /designs/digital_control_top/subdesigns/dig_i2c_fsm
::legacy::set_attribute -quiet hdl_user_name dig_i2c_fsm /designs/digital_control_top/subdesigns/dig_i2c_fsm
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_i2c_fsm.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_i2c_fsm
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_i2c_fsm
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/subports_in/DFT_sdi
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/I_dig_i2c_fsm/subports_in/DFT_sen
::legacy::set_attribute -quiet hdl_user_name dig_i2c_vedge /designs/digital_control_top/subdesigns/dig_i2c_vedge
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_i2c_vedge.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_i2c_vedge
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_i2c_vedge
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/start_detect/subports_in/DFT_sdi
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/start_detect/subports_in/DFT_sen
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/start_detect/subports_out/DFT_sdo
::legacy::set_attribute -quiet hdl_user_name dig_i2c_vedge /designs/digital_control_top/subdesigns/dig_i2c_vedge_443
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_i2c_vedge.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_i2c_vedge_443
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_i2c_vedge_443
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/stop_detect/subports_in/DFT_sdi
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/stop_detect/subports_in/DFT_sen
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_i2c/instances_hier/stop_detect/subports_out/DFT_sdo
::legacy::set_attribute -quiet hdl_user_name dig_io_control /designs/digital_control_top/subdesigns/dig_io_control
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_io_control.v} {$BLOCK_PATH/rtl_v}} {default -v2001 {SYNTHESIS} {../../rtl_v/dig_deb.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_io_control
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_io_control
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_io_control/subports_in/DFT_sdi
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_io_control/subports_in/DFT_sen
::legacy::set_attribute -quiet hdl_user_name dig_deb /designs/digital_control_top/subdesigns/dig_deb_WIDTH4_RESET1h0_1
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_deb.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_deb_WIDTH4_RESET1h0_1
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_deb_WIDTH4_RESET1h0_1
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_io_control/instances_hier/dig_deb_en_in/subports_in/DFT_sdi
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_io_control/instances_hier/dig_deb_en_in/subports_in/DFT_sen
::legacy::set_attribute -quiet hdl_user_name dig_deb /designs/digital_control_top/subdesigns/dig_deb_WIDTH3_RESET1h0_2
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_deb.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_deb_WIDTH3_RESET1h0_2
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_deb_WIDTH3_RESET1h0_2
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_io_control/instances_hier/dig_deb_sync_in/subports_in/DFT_sdi
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_io_control/instances_hier/dig_deb_sync_in/subports_in/DFT_sen
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_io_control/instances_hier/dig_deb_sync_in/subports_out/DFT_sdo
::legacy::set_attribute -quiet is_sop_cluster true /designs/digital_control_top/subdesigns/dig_main_fsm
::legacy::set_attribute -quiet hdl_user_name dig_main_fsm /designs/digital_control_top/subdesigns/dig_main_fsm
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_main_fsm.v} {$BLOCK_PATH/rtl_v}} {default -v2001 {SYNTHESIS} {../../rtl_v/dig_deb_pos.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_main_fsm
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_main_fsm
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_main_fsm/subports_in/DFT_sen
::legacy::set_attribute -quiet hdl_user_name dig_deb_pos /designs/digital_control_top/subdesigns/dig_deb_pos_WIDTH4_RESET1h1
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_deb_pos.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_deb_pos_WIDTH4_RESET1h1
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_deb_pos_WIDTH4_RESET1h1
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_hier/I_deb_prot_pulse/subports_in/DFT_sdi
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_hier/I_deb_prot_pulse/subports_in/DFT_sen
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_main_fsm/instances_hier/I_deb_prot_pulse/subports_out/DFT_sdo
::legacy::set_attribute -quiet hdl_user_name dig_regs /designs/digital_control_top/subdesigns/dig_regs
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_regs.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_regs
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_regs
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_regs/subports_in/DFT_sdi
::legacy::set_attribute -quiet dft_auto_created 1 /designs/digital_control_top/instances_hier/i_dig_regs/subports_in/DFT_sen
::legacy::set_attribute -quiet hdl_user_name dig_scan_mux /designs/digital_control_top/subdesigns/dig_scan_mux
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_cgc.v} {$BLOCK_PATH/rtl_v}} {default -v2001 {SYNTHESIS} {../../rtl_v/dig_scan_mux.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_scan_mux
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_scan_mux
::legacy::set_attribute -quiet preserve const_prop_size_delete_ok /designs/digital_control_top/instances_hier/i_dig_scan_mux/instances_comb/g26
::legacy::set_attribute -quiet hdl_user_name dig_cgc /designs/digital_control_top/subdesigns/dig_cgc_21
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_cgc.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_cgc_21
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_cgc_21
::legacy::set_attribute -quiet hdl_user_name dig_scan_wrapper /designs/digital_control_top/subdesigns/dig_scan_wrapper
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_scan_wrapper.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_scan_wrapper
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_scan_wrapper
::legacy::set_attribute -quiet hdl_user_name dig_test_mux /designs/digital_control_top/subdesigns/dig_test_mux
::legacy::set_attribute -quiet hdl_filelist {{default -v2001 {SYNTHESIS} {../../rtl_v/dig_test_mux.v} {$BLOCK_PATH/rtl_v}}} /designs/digital_control_top/subdesigns/dig_test_mux
::legacy::set_attribute -quiet ungroup_ok false /designs/digital_control_top/subdesigns/dig_test_mux
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop105
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop105
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop88
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop88
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop82
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop82
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop86
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop86
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop90
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop90
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop78
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop78
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop84
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop84
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop93
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop93
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop94
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop94
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop110
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop110
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop100
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop100
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop91
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop91
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop92
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop92
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop109
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop109
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop95
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop95
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop96
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop96
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop97
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop97
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop99
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop99
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop101
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop101
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop80
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop80
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop103
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop103
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop106
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop106
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop108
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop108
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop112
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop112
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop113
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop113
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop104
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop104
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop107
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop107
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop111
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop111
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop102
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop102
::legacy::set_attribute -quiet dft_auto_created testpoint /designs/digital_control_top/instances_seq/DFT_tpi_flop98
::legacy::set_attribute -quiet preserve map_size_ok /designs/digital_control_top/instances_seq/DFT_tpi_flop98
# BEGIN PHYSICAL ANNOTATION SECTION
# END PHYSICAL ANNOTATION SECTION
check_dft_rules /designs/digital_control_top
