REGISTERS:	 Address(Hex)	W/R	Values(Hex)	Table	W_D7	W_D6	W_D5	W_D4	W_D3	W_D2	W_D1	W_D0	R_D7	R_D6	R_D5	R_D4	R_D3	R_D2	R_D1	R_D0
0 - STATUS	0	R	0		ildo_stat	vth_stat	oca_stat	ota_stat	tsd_stat	adc_eoc_stat	ova_stat	chg_ok_stat	ildo_stat	vth_stat	oca_stat	ota_stat	tsd_stat	adc_eoc_stat	ova_stat	chg_ok_stat
1 - VIN	1	R	0	 [7:0]	vin_7	vin_6	vin_5	vin_4	vin_3	vin_2	vin_1	vin_0	vin_7	vin_6	vin_5	vin_4	vin_3	vin_2	vin_1	vin_0
2 - IIN	2	R	0	 [7:0]	iin_7	iin_6	iin_5	iin_4	iin_3	iin_2	iin_1	iin_0	iin_7	iin_6	iin_5	iin_4	iin_3	iin_2	iin_1	iin_0
3 - TEMP	3	R	0	 [7:0]	temp_7	temp_6	temp_5	temp_4	temp_3	temp_2	temp_1	temp_0	temp_7	temp_6	temp_5	temp_4	temp_3	temp_2	temp_1	temp_0
4 - CMD1	4	RW	43	 [6:4] [3:0]	unused	vcl_2	vcl_1	vcl_0	vth_3	vth_2	vth_1	vth_0	unused	vcl_2	vcl_1	vcl_0	vth_3	vth_2	vth_1	vth_0
5 - CMD2	5	RW	29	 [7:5] [4:3]	div2_dly_2	div2_dly_1	div2_dly_0	conv_period_1	conv_period_0	clo_dis	pwr_ok	unused	div2_dly_2	div2_dly_1	div2_dly_0	conv_period_1	conv_period_0	clo_dis	pwr_ok	unused
6 - CMD3	6	RW	2	 [1:0]	unused	unused	unused	unused	adc_manual	adc_request	vldo_1	vldo_0	unused	unused	unused	unused	adc_manual	adc_request	vldo_1	vldo_0
7 - SNS1	7	R	0		ildo_sns	vth_sns	oca_sns	ota_sns	tsd_sns	adc_eoc_sns	ova_sns	chg_ok_sns	ildo_sns	vth_sns	oca_sns	ota_sns	tsd_sns	adc_eoc_sns	ova_sns	chg_ok_sns
8 - SNS2	8	R	0	 [5:2]	unused	unused	n_cli_3	n_cli_2	n_cli_1	n_cli_0	unused	unused	unused	unused	n_cli_3	n_cli_2	n_cli_1	n_cli_0	unused	unused
9 - INTERRUPTS	9	R	0		ildo_int	vth_int	oca_int	ota_int	tsd_int	adc_eoc_int	ova_int	chg_ok_int	ildo_int	vth_int	oca_int	ota_int	tsd_int	adc_eoc_int	ova_int	chg_ok_int
A - ID	A	R	0	 [7:0]	rev_id_7	rev_id_6	rev_id_5	rev_id_4	rev_id_3	rev_id_2	rev_id_1	rev_id_0	rev_id_7	rev_id_6	rev_id_5	rev_id_4	rev_id_3	rev_id_2	rev_id_1	rev_id_0
2E - TEST_REGISTER0	2E	RW	0	 [2:0]	test_mode_sns	scan_mode_sel	test_state	fast_clk	tb_force_uvlob	cp_state_2	cp_state_1	cp_state_0	test_mode_sns	scan_mode_sel	test_state	fast_clk	tb_force_uvlob	cp_state_2	cp_state_1	cp_state_0
2F - TEST_REGISTER1	2F	RW	0	 [2:1]	tb_no_wait_state	tb_tsd_blk	tb_no_ldo_ishort	tb_vldo_dischg_dis	tb_force_clo_in	tb_clk_div2_1	tb_clk_div2_0	tb_clk_pt_dis	tb_no_wait_state	tb_tsd_blk	tb_no_ldo_ishort	tb_vldo_dischg_dis	tb_force_clo_in	tb_clk_div2_1	tb_clk_div2_0	tb_clk_pt_dis
30 - TEST_REGISTER2	30	RW	0	 [7:5]	tb_refs_2	tb_refs_1	tb_refs_0	tb_osc_byp	tb_force_vref_startup	tb_spare1	tb_spare2	unused	tb_refs_2	tb_refs_1	tb_refs_0	tb_osc_byp	tb_force_vref_startup	tb_spare1	tb_spare2	unused
31 - TEST_REGISTER3	31	RW	0	 [4:3]	unused	tb_adc_signed	tb_adc_dft_config	tb_adc_channel_1	tb_adc_channel_0	tb_adc_az_dis	tb_adc_ext_vref	unused	unused	tb_adc_signed	tb_adc_dft_config	tb_adc_channel_1	tb_adc_channel_0	tb_adc_az_dis	tb_adc_ext_vref	unused
32 - TEST_REGISTER4	32	R	0	 [6:0]	adc_data_sign	adc_data_msb_6	adc_data_msb_5	adc_data_msb_4	adc_data_msb_3	adc_data_msb_2	adc_data_msb_1	adc_data_msb_0	adc_data_sign	adc_data_msb_6	adc_data_msb_5	adc_data_msb_4	adc_data_msb_3	adc_data_msb_2	adc_data_msb_1	adc_data_msb_0
33 - TEST_REGISTER5	33	RW	10	 [7:5] [4:2]	adc_data_lsb_2	adc_data_lsb_1	adc_data_lsb_0	tb_adc_hold_delay_2	tb_adc_hold_delay_1	tb_adc_hold_delay_0	en_fuse_bypass	tb_en_fuse_curr_sink	adc_data_lsb_2	adc_data_lsb_1	adc_data_lsb_0	tb_adc_hold_delay_2	tb_adc_hold_delay_1	tb_adc_hold_delay_0	en_fuse_bypass	tb_en_fuse_curr_sink
34 - TEST_REGISTER6	34	RW	0	 [6:4] [2:0]	en_test_mux1	test_mux1_ctrl_2	test_mux1_ctrl_1	test_mux1_ctrl_0	en_test_mux2	test_mux2_ctrl_2	test_mux2_ctrl_1	test_mux2_ctrl_0	en_test_mux1	test_mux1_ctrl_2	test_mux1_ctrl_1	test_mux1_ctrl_0	en_test_mux2	test_mux2_ctrl_2	test_mux2_ctrl_1	test_mux2_ctrl_0
35 - TEST_REGISTER7	35	RW	0	 [7:2]	dig_mux_5	dig_mux_4	dig_mux_3	dig_mux_2	dig_mux_1	dig_mux_0	tb_digmux_clo	unused	dig_mux_5	dig_mux_4	dig_mux_3	dig_mux_2	dig_mux_1	dig_mux_0	tb_digmux_clo	unused
36 - TEST_REGISTER8	36	RW	60		en_output_wrapper	wrap_en_tsd	wrap_clk_12Mhz_en	wrap_en_vin_monitor	wrap_en_clo_det	wrap_en_vldo	wrap_en_vin_meter	wrap_en_iin_meter	en_output_wrapper	wrap_en_tsd	wrap_clk_12Mhz_en	wrap_en_vin_monitor	wrap_en_clo_det	wrap_en_vldo	wrap_en_vin_meter	wrap_en_iin_meter
37 - TEST_REGISTER9	37	RW	0		wrap_cp_pass_thru	wrap_cp_wait	wrap_cp_div2	wrap_cp_tsd	wrap_en_cp	wrap_cp_en_pmos	wrap_en_vin_vcl	unused	wrap_cp_pass_thru	wrap_cp_wait	wrap_cp_div2	wrap_cp_tsd	wrap_en_cp	wrap_cp_en_pmos	wrap_en_vin_vcl	unused
38 - TRIM0	38	RW	0	 [7:0]	otp_7	otp_6	otp_5	otp_4	otp_3	otp_2	otp_1	otp_0	otp_7	otp_6	otp_5	otp_4	otp_3	otp_2	otp_1	otp_0
39 - TRIM1	39	RW	0	 [7:0]	otp_15	otp_14	otp_13	otp_12	otp_11	otp_10	otp_9	otp_8	otp_15	otp_14	otp_13	otp_12	otp_11	otp_10	otp_9	otp_8
3A - TRIM2	3A	RW	0	 [7:0]	otp_23	otp_22	otp_21	otp_20	otp_19	otp_18	otp_17	otp_16	otp_23	otp_22	otp_21	otp_20	otp_19	otp_18	otp_17	otp_16
3B - TRIM3	3B	RW	0	 [7:0]	otp_31	otp_30	otp_29	otp_28	otp_27	otp_26	otp_25	otp_24	otp_31	otp_30	otp_29	otp_28	otp_27	otp_26	otp_25	otp_24
3C - TRIM4	3C	R	0	 [7:0]	otp_39	otp_38	otp_37	otp_36	otp_35	otp_34	otp_33	otp_32	otp_39	otp_38	otp_37	otp_36	otp_35	otp_34	otp_33	otp_32
3D - TRIM5	3D	R	0	 [7:0]	otp_47	otp_46	otp_45	otp_44	otp_43	otp_42	otp_41	otp_40	otp_47	otp_46	otp_45	otp_44	otp_43	otp_42	otp_41	otp_40
3E - TRIM6	3E	R	0	 [7:0]	otp_55	otp_54	otp_53	otp_52	otp_51	otp_50	otp_49	otp_48	otp_55	otp_54	otp_53	otp_52	otp_51	otp_50	otp_49	otp_48
3F - TRIM7	3F	R	0	 [7:0]	otp_63	otp_62	otp_61	otp_60	otp_59	otp_58	otp_57	otp_56	otp_63	otp_62	otp_61	otp_60	otp_59	otp_58	otp_57	otp_56
40 - TRIMCMD	40	RW	0	 [6:5]	otp_emul_zero	cursen_1	cursen_0	readback	otp_sel	re_latch	hw	sw	otp_emul_zero	cursen_1	cursen_0	readback	otp_sel	re_latch	hw	sw
REGISTERS END
