# Reading D:/Logiciels/EDA/intelFPGA/17.0/modelsim_ase/tcl/vsim/pref.tcl
# Loading project Patrice
vsim work.toto
# vsim work.toto 
# Start time: 09:26:08 on Nov 26,2017
# Loading sv_std.std
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(93): [PCDPC] - Port size (8) does not match connection size (1) for port 'out'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(93): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(93): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(93): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(93): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(93): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(93): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(104): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(12).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(104): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(16).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(104): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(104): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(104): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(104): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(104): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(104): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(104): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(104): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(104): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(35): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(104).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
add wave -position insertpoint  \
sim:/toto/conv_data \
sim:/toto/REF \
sim:/toto/clk_1us \
sim:/toto/rstb \
sim:/toto/eoc \
sim:/toto/dac_conv \
sim:/toto/ON \
sim:/toto/clk_1ms \
sim:/toto/en_sequencer \
sim:/toto/testmode \
sim:/toto/adc_pd \
sim:/toto/enable_sar \
sim:/toto/X \
sim:/toto/out \
sim:/toto/in0 \
sim:/toto/in1 \
sim:/toto/in2 \
sim:/toto/in3 \
sim:/toto/in4 \
sim:/toto/select \
sim:/toto/adc_data \
sim:/toto/enable_SAR \
sim:/toto/channel_mux_ctrl \
sim:/toto/range_mux_ctrl \
sim:/toto/ch1_range1_data \
sim:/toto/ch1_range2_data \
sim:/toto/ch1_range3_data \
sim:/toto/ch2_data \
sim:/toto/ch3_data \
sim:/toto/ch4_data \
sim:/toto/ch5_data \
sim:/toto/test_mux_data_conv \
sim:/toto/acq_cycle_done
quit -sim
# End time: 09:27:02 on Nov 26,2017, Elapsed time: 0:00:54
# Errors: 0, Warnings: 19
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# 10 compiles, 0 failed with no errors.
vsim work.toto
# vsim work.toto 
# Start time: 09:28:03 on Nov 26,2017
# Loading sv_std.std
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(93): [PCDPC] - Port size (8) does not match connection size (1) for port 'out'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(93): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(93): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(93): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(93): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(93): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(93): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(104): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(12).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(104): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(16).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(104): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(104): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(104): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(104): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(104): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(104): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(104): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(104): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(104): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(35): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(104).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
add wave -position insertpoint  \
sim:/toto/conv_data \
sim:/toto/REF \
sim:/toto/clk_1us \
sim:/toto/rstb \
sim:/toto/eoc \
sim:/toto/dac_conv \
sim:/toto/ON \
sim:/toto/clk_1ms \
sim:/toto/en_sequencer \
sim:/toto/testmode \
sim:/toto/adc_pd \
sim:/toto/enable_sar \
sim:/toto/X \
sim:/toto/out \
sim:/toto/in0 \
sim:/toto/in1 \
sim:/toto/in2 \
sim:/toto/in3 \
sim:/toto/in4 \
sim:/toto/select \
sim:/toto/adc_data \
sim:/toto/enable_SAR \
sim:/toto/channel_mux_ctrl \
sim:/toto/range_mux_ctrl \
sim:/toto/ch1_range1_data \
sim:/toto/ch1_range2_data \
sim:/toto/ch1_range3_data \
sim:/toto/ch2_data \
sim:/toto/ch3_data \
sim:/toto/ch4_data \
sim:/toto/ch5_data \
sim:/toto/test_mux_data_conv \
sim:/toto/acq_cycle_done
run -all
run -all
run -all
run -all
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# 10 compiles, 0 failed with no errors.
restart -f
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'out'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(12).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(16).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(35): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
run -all
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# 10 compiles, 0 failed with no errors.
restart -f
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'out'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(12).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(16).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(35): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
run -all
# WARNING: No extended dataflow license exists
# Compile of sequencer.v failed with 1 errors.
# Compile of sequencer.v failed with 2 errors.
# Compile of sequencer.v failed with 1 errors.
# Compile of sequencer.v was successful.
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# 10 compiles, 0 failed with no errors.
restart -f
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'out'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(12).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(16).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(35): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
# Warning in wave window restart: (vish-4014) No objects found matching '/toto/enable_SAR'. 
# Break key hit
quit -sim
# End time: 09:59:08 on Nov 26,2017, Elapsed time: 0:31:05
# Errors: 1, Warnings: 77
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# 10 compiles, 0 failed with no errors.
vsim work.toto
# vsim work.toto 
# Start time: 09:59:27 on Nov 26,2017
# Loading sv_std.std
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(87): [PCDPC] - Port size (8) does not match connection size (1) for port 'REF'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/ana_adc.v(6).
#    Time: 0 ps  Iteration: 0  Instance: /toto/ana_adc File: D:/Logiciels/EDA/intelFPGA/17.0/ana_adc.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'out'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(12).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(16).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(35): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
add wave -position insertpoint  \
sim:/toto/X
add wave -position insertpoint  \
sim:/toto/conv_data \
sim:/toto/REF \
sim:/toto/clk_1us \
sim:/toto/rstb \
sim:/toto/eoc \
sim:/toto/dac_conv \
sim:/toto/ON \
sim:/toto/clk_1ms \
sim:/toto/en_sequencer \
sim:/toto/testmode \
sim:/toto/adc_pd \
sim:/toto/enable_sar \
sim:/toto/X \
sim:/toto/out \
sim:/toto/in0 \
sim:/toto/in1 \
sim:/toto/in2 \
sim:/toto/in3 \
sim:/toto/in4 \
sim:/toto/select \
sim:/toto/adc_data \
sim:/toto/range_mux_ctrl \
sim:/toto/ch1_range1_data \
sim:/toto/ch1_range2_data \
sim:/toto/ch1_range3_data \
sim:/toto/ch2_data \
sim:/toto/ch3_data \
sim:/toto/ch4_data \
sim:/toto/ch5_data \
sim:/toto/test_mux_data_conv \
sim:/toto/acq_cycle_done
run -all
add wave -position insertpoint  \
sim:/toto/sequencer/state
restart -f
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(87): [PCDPC] - Port size (8) does not match connection size (1) for port 'REF'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/ana_adc.v(6).
#    Time: 0 ps  Iteration: 0  Instance: /toto/ana_adc File: D:/Logiciels/EDA/intelFPGA/17.0/ana_adc.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'out'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(12).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(16).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(35): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
run -all
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# 10 compiles, 0 failed with no errors.
restart -f
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(87): [PCDPC] - Port size (8) does not match connection size (1) for port 'REF'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/ana_adc.v(6).
#    Time: 0 ps  Iteration: 0  Instance: /toto/ana_adc File: D:/Logiciels/EDA/intelFPGA/17.0/ana_adc.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'out'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(12).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(16).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(35): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
run -all
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v failed with 1 errors.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# 10 compiles, 1 failed with 1 error.
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v failed with 1 errors.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# 10 compiles, 1 failed with 1 error.
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# 10 compiles, 0 failed with no errors.
restart -f
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(87): [PCDPC] - Port size (8) does not match connection size (1) for port 'REF'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/ana_adc.v(6).
#    Time: 0 ps  Iteration: 0  Instance: /toto/ana_adc File: D:/Logiciels/EDA/intelFPGA/17.0/ana_adc.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'out'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(12).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(16).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(35): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
run -all
quit -sim
# End time: 10:20:04 on Nov 26,2017, Elapsed time: 0:20:37
# Errors: 0, Warnings: 80
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# 10 compiles, 0 failed with no errors.
vsim work.toto
# vsim work.toto 
# Start time: 10:20:27 on Nov 26,2017
# Loading sv_std.std
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(87): [PCDPC] - Port size (8) does not match connection size (1) for port 'REF'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/ana_adc.v(6).
#    Time: 0 ps  Iteration: 0  Instance: /toto/ana_adc File: D:/Logiciels/EDA/intelFPGA/17.0/ana_adc.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'out'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(12).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(16).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(35): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
add wave -position insertpoint  \
sim:/toto/sequencer/counter
add wave -position insertpoint  \
sim:/toto/sequencer/state
add wave -position insertpoint  \
sim:/toto/sequencer/channel
add wave -position insertpoint  \
sim:/toto/sequencer/enable_sar
add wave -position insertpoint  \
sim:/toto/conv_data \
sim:/toto/REF \
sim:/toto/clk_1us \
sim:/toto/rstb \
sim:/toto/eoc \
sim:/toto/dac_conv \
sim:/toto/ON \
sim:/toto/clk_1ms \
sim:/toto/en_sequencer \
sim:/toto/testmode \
sim:/toto/adc_pd \
sim:/toto/enable_sar \
sim:/toto/X \
sim:/toto/out \
sim:/toto/in0 \
sim:/toto/in1 \
sim:/toto/in2 \
sim:/toto/in3 \
sim:/toto/in4 \
sim:/toto/select \
sim:/toto/adc_data \
sim:/toto/range_mux_ctrl \
sim:/toto/ch1_range1_data \
sim:/toto/ch1_range2_data \
sim:/toto/ch1_range3_data \
sim:/toto/ch2_data \
sim:/toto/ch3_data \
sim:/toto/ch4_data \
sim:/toto/ch5_data \
sim:/toto/test_mux_data_conv \
sim:/toto/acq_cycle_done
run -all
add wave -position insertpoint  \
sim:/toto/sequencer/testmode
restart -f
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(87): [PCDPC] - Port size (8) does not match connection size (1) for port 'REF'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/ana_adc.v(6).
#    Time: 0 ps  Iteration: 0  Instance: /toto/ana_adc File: D:/Logiciels/EDA/intelFPGA/17.0/ana_adc.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'out'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(12).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(16).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(35): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
run -all
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v failed with 1 errors.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# 10 compiles, 1 failed with 1 error.
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# 10 compiles, 0 failed with no errors.
restart -f
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(87): [PCDPC] - Port size (8) does not match connection size (1) for port 'REF'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/ana_adc.v(6).
#    Time: 0 ps  Iteration: 0  Instance: /toto/ana_adc File: D:/Logiciels/EDA/intelFPGA/17.0/ana_adc.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'out'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(12).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(16).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(35): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
add wave -position insertpoint  \
sim:/toto/sequencer/testmode
add wave -position insertpoint  \
sim:/toto/sequencer/counter
add wave -position insertpoint  \
sim:/toto/sequencer/counter
add wave -position insertpoint  \
sim:/toto/sequencer/adc_pd
add wave -position insertpoint  \
sim:/toto/sequencer/testmode
run -all
add wave -position insertpoint  \
sim:/toto/sequencer/state
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# 10 compiles, 0 failed with no errors.
restart -f
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(87): [PCDPC] - Port size (8) does not match connection size (1) for port 'REF'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/ana_adc.v(6).
#    Time: 0 ps  Iteration: 0  Instance: /toto/ana_adc File: D:/Logiciels/EDA/intelFPGA/17.0/ana_adc.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'out'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(95): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(12).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(16).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(35): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(106).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
run -all
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# 10 compiles, 0 failed with no errors.
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# 10 compiles, 0 failed with no errors.
restart -f
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(89): [PCDPC] - Port size (8) does not match connection size (1) for port 'REF'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/ana_adc.v(6).
#    Time: 0 ps  Iteration: 0  Instance: /toto/ana_adc File: D:/Logiciels/EDA/intelFPGA/17.0/ana_adc.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(97): [PCDPC] - Port size (8) does not match connection size (1) for port 'out'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(97): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(97): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(97): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(97): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(97): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(97): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(108): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(12).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(108): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(16).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(108): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(108): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(108): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(108): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(108): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(108): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(108): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(108): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(108): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(37): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(108).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
# Warning in wave window restart: (vish-4014) No objects found matching '/toto/dac_conv'. 
# Warning in wave window restart: (vish-4014) No objects found matching '/toto/out'. 
quit -sim
# End time: 10:54:44 on Nov 26,2017, Elapsed time: 0:34:17
# Errors: 2, Warnings: 100
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# 10 compiles, 0 failed with no errors.
vsim work.toto
# vsim work.toto 
# Start time: 10:55:12 on Nov 26,2017
# Loading sv_std.std
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(89): [PCDPC] - Port size (8) does not match connection size (1) for port 'REF'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/ana_adc.v(6).
#    Time: 0 ps  Iteration: 0  Instance: /toto/ana_adc File: D:/Logiciels/EDA/intelFPGA/17.0/ana_adc.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(97): [PCDPC] - Port size (8) does not match connection size (1) for port 'out'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(97): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(97): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(97): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(97): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(97): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(97): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(108): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(12).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(108): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(16).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(108): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(108): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(108): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(108): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(108): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(108): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(108): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(108): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(108): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(37): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(108).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
add wave -position insertpoint  \
sim:/toto/conv_data \
sim:/toto/REF \
sim:/toto/clk_1us \
sim:/toto/rstb \
sim:/toto/eoc \
sim:/toto/mux_channel \
sim:/toto/dac_data \
sim:/toto/ON \
sim:/toto/clk_1ms \
sim:/toto/en_sequencer \
sim:/toto/testmode \
sim:/toto/adc_pd \
sim:/toto/enable_sar \
sim:/toto/X \
sim:/toto/in0 \
sim:/toto/in1 \
sim:/toto/in2 \
sim:/toto/in3 \
sim:/toto/in4 \
sim:/toto/select \
sim:/toto/adc_data \
sim:/toto/range_mux_ctrl \
sim:/toto/ch1_range1_data \
sim:/toto/ch1_range2_data \
sim:/toto/ch1_range3_data \
sim:/toto/ch2_data \
sim:/toto/ch3_data \
sim:/toto/ch4_data \
sim:/toto/ch5_data \
sim:/toto/test_mux_data_conv \
sim:/toto/acq_cycle_done
add wave -position insertpoint  \
sim:/toto/sequencer/enable_sar \
sim:/toto/sequencer/adc_pd
add wave -position insertpoint  \
sim:/toto/sequencer/en_sequencer \
sim:/toto/sequencer/testmode
add wave -position insertpoint  \
sim:/toto/sequencer/state \
sim:/toto/sequencer/channel \
sim:/toto/sequencer/counter
add wave -position insertpoint  \
sim:/toto/sequencer/acq_cycle_done
run -all
# Compile of sar_bis.v was successful.
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# 11 compiles, 0 failed with no errors.
restart -f
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(12).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(16).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(37): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
restart -f
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(12).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(16).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(37): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
run -all
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# 11 compiles, 0 failed with no errors.
restart -f
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(12).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(16).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(37): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
run -all
add wave -position insertpoint  \
sim:/toto/sar/state
restart -f
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(12).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(16).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(37): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
run -all
add wave -position insertpoint  \
sim:/toto/sar/counter
run -all
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# 11 compiles, 0 failed with no errors.
restart -f
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(13).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(26).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(37): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
add wave -position insertpoint  \
sim:/toto/sequencer/clk_cycle
run -all
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# 11 compiles, 0 failed with no errors.
restart -f
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(13).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(26).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(37): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
run -all
# Compile of edge_detect.v was successful.
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# 12 compiles, 0 failed with no errors.
restart -f
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(13).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(26).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(37): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
run -all
add wave -position insertpoint  \
sim:/toto/sequencer/cycle_on
restart -f
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(13).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(26).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(37): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
run -all
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# 12 compiles, 0 failed with no errors.
restart -f
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(13).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(26).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(37): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
run -all
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# 12 compiles, 0 failed with no errors.
restart -f
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(13).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(26).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(37): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
run -all
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# 12 compiles, 0 failed with no errors.
restart -f
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(13).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(26).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(37): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
run -all
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# 12 compiles, 0 failed with no errors.
restart -f
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(13).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(26).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(37): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
run -all
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# 12 compiles, 0 failed with no errors.
restart -f
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(100): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(13).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(26).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(37): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(111).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
run -all
# ** Note: $finish    : D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(72)
#    Time: 226 us  Iteration: 2  Instance: /toto
# 1
# Break in Module toto at D:/Logiciels/EDA/intelFPGA/17.0/toto.sv line 72
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# 12 compiles, 0 failed with no errors.
restart -f
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(102): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(102): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(102): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(102): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(102): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(102): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(13).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(26).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(37): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
run -all
# ** Note: $finish    : D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(74)
#    Time: 4186 us  Iteration: 2  Instance: /toto
# 1
# Break in Module toto at D:/Logiciels/EDA/intelFPGA/17.0/toto.sv line 74
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# 12 compiles, 0 failed with no errors.
restart -f
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(102): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(102): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(102): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(102): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(102): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(102): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(13).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(26).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(37): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
run -all
# ** Note: $finish    : D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(74)
#    Time: 4186 us  Iteration: 2  Instance: /toto
# 1
# Break in Module toto at D:/Logiciels/EDA/intelFPGA/17.0/toto.sv line 74
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v failed with 1 errors.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# 12 compiles, 1 failed with 1 error.
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v failed with 1 errors.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# 12 compiles, 1 failed with 1 error.
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v failed with 1 errors.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# 12 compiles, 1 failed with 1 error.
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# 12 compiles, 0 failed with no errors.
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v failed with 1 errors.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# 12 compiles, 1 failed with 1 error.
# Unrecognized paper size (Letter), using Custom
# Unrecognized paper size (Letter), using Custom
# Unrecognized paper size (Letter), using Custom
# Unrecognized paper size (Letter), using Custom
# Unrecognized paper size (0), using Custom
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# 12 compiles, 0 failed with no errors.
restart -f
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(102): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(102): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(102): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(102): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(102): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(102): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(13).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(26).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(37): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
run -all
# ** Note: $finish    : D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(74)
#    Time: 4186 us  Iteration: 2  Instance: /toto
# 1
# Break in Module toto at D:/Logiciels/EDA/intelFPGA/17.0/toto.sv line 74
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# 12 compiles, 0 failed with no errors.
restart -f
# Loading work.toto
# Loading work.sar
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(102): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(102): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(102): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(102): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(102): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(102): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(13).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(26).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(37): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(113).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
run -all
# ** Note: $finish    : D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(74)
#    Time: 4186 us  Iteration: 2  Instance: /toto
# 1
# Break in Module toto at D:/Logiciels/EDA/intelFPGA/17.0/toto.sv line 74
quit -sim
# End time: 17:09:18 on Nov 26,2017, Elapsed time: 6:14:06
# Errors: 5, Warnings: 326
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v failed with 1 errors.
# Compile of edge_detect.v was successful.
# 12 compiles, 1 failed with 1 error.
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# 12 compiles, 0 failed with no errors.
vsim work.toto
# vsim work.toto 
# Start time: 17:15:49 on Nov 26,2017
# Loading sv_std.std
# Loading work.toto
# Loading work.sar_bis
# Loading work.ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(114): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(114): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(114): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(114): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(114): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(114): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /toto/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(125): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(13).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(125): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(125): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(125): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(125): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(125): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(125): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(125): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(125): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(125): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(125): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(26).
#    Time: 0 ps  Iteration: 0  Instance: /toto/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(37): Variable '/toto/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(125).
#    Time: 0 ps  Iteration: 0  Instance: /toto File: D:/Logiciels/EDA/intelFPGA/17.0/toto.sv
add wave -position insertpoint  \
sim:/toto/conv_data \
sim:/toto/REF \
sim:/toto/clk_1us \
sim:/toto/rstb \
sim:/toto/eoc \
sim:/toto/mux_channel \
sim:/toto/dac_data \
sim:/toto/ON \
sim:/toto/clk_1ms \
sim:/toto/en_sequencer \
sim:/toto/testmode \
sim:/toto/adc_pd \
sim:/toto/enable_sar \
sim:/toto/X \
sim:/toto/in0 \
sim:/toto/in1 \
sim:/toto/in2 \
sim:/toto/in3 \
sim:/toto/in4 \
sim:/toto/select \
sim:/toto/adc_data \
sim:/toto/range_mux_ctrl \
sim:/toto/ch1_range1_data \
sim:/toto/ch1_range2_data \
sim:/toto/ch1_range3_data \
sim:/toto/ch2_data \
sim:/toto/ch3_data \
sim:/toto/ch4_data \
sim:/toto/ch5_data \
sim:/toto/test_mux_data_conv \
sim:/toto/acq_cycle_done
run -all
# ** Note: $finish    : D:/Logiciels/EDA/intelFPGA/17.0/toto.sv(74)
#    Time: 4186 us  Iteration: 2  Instance: /toto
# 1
# Break in Module toto at D:/Logiciels/EDA/intelFPGA/17.0/toto.sv line 74
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv failed with 1 errors.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# 12 compiles, 1 failed with 1 error.
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# 12 compiles, 0 failed with no errors.
restart -f
# Loading work.toto
# Loading work.sar_bis
# Loading work.ana_adc
# Warning in wave window restart: (vish-4014) No objects found matching '/toto/enable_sar'. 
# Warning in wave window restart: (vish-4014) No objects found matching '/toto/in0'. 
# Warning in wave window restart: (vish-4014) No objects found matching '/toto/in1'. 
# Warning in wave window restart: (vish-4014) No objects found matching '/toto/in2'. 
# Warning in wave window restart: (vish-4014) No objects found matching '/toto/in3'. 
# Warning in wave window restart: (vish-4014) No objects found matching '/toto/in4'. 
# Warning in wave window restart: (vish-4014) No objects found matching '/toto/select'. 
# Warning in wave window restart: (vish-4014) No objects found matching '/toto/adc_data'. 
# Warning in wave window restart: (vish-4014) No objects found matching '/toto/range_mux_ctrl'. 
# Warning in wave window restart: (vish-4014) No objects found matching '/toto/ch1_range1_data'. 
# Warning in wave window restart: (vish-4014) No objects found matching '/toto/ch1_range2_data'. 
# Warning in wave window restart: (vish-4014) No objects found matching '/toto/ch1_range3_data'. 
# Warning in wave window restart: (vish-4014) No objects found matching '/toto/ch2_data'. 
# Warning in wave window restart: (vish-4014) No objects found matching '/toto/ch3_data'. 
# Warning in wave window restart: (vish-4014) No objects found matching '/toto/ch4_data'. 
# Warning in wave window restart: (vish-4014) No objects found matching '/toto/ch5_data'. 
# Warning in wave window restart: (vish-4014) No objects found matching '/toto/test_mux_data_conv'. 
# Warning in wave window restart: (vish-4014) No objects found matching '/toto/acq_cycle_done'. 
run -all
run -all
run -all
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# 12 compiles, 0 failed with no errors.
restart -f
# Loading work.toto
# Loading work.sar_bis
# Loading work.ana_adc
run -all
run -all
run -all
# Compile of keboda_testbench.sv was successful.
# Compile of keboda_ana_adc.v was successful.
quit -sim
# End time: 17:26:23 on Nov 26,2017, Elapsed time: 0:10:34
# Errors: 18, Warnings: 18
# Compile of keboda_testbench.sv failed with 1 errors.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v was successful.
# 3 compiles, 1 failed with 1 error.
# Compile of keboda_testbench.sv was successful.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v was successful.
# 3 compiles, 0 failed with no errors.
vsim work.keboda_testbench
# vsim work.keboda_testbench 
# Start time: 17:29:19 on Nov 26,2017
# Loading sv_std.std
# Loading work.keboda_testbench
# Loading work.keboda_sar
# Loading work.keboda_ana_adc
add wave -position insertpoint  \
sim:/keboda_testbench/A \
sim:/keboda_testbench/DATA_HOLD \
sim:/keboda_testbench/REF \
sim:/keboda_testbench/CK \
sim:/keboda_testbench/RSTB \
sim:/keboda_testbench/EOC \
sim:/keboda_testbench/START_CONV \
sim:/keboda_testbench/MSB_therm_code \
sim:/keboda_testbench/LSB_code \
sim:/keboda_testbench/ON \
sim:/keboda_testbench/lilipipo \
sim:/keboda_testbench/X
run -all
run -all
# Compile of keboda_testbench.sv was successful.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v failed with 2 errors.
# 3 compiles, 1 failed with 2 errors.
# Compile of keboda_testbench.sv was successful.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v failed with 2 errors.
# 3 compiles, 1 failed with 2 errors.
# Compile of keboda_testbench.sv was successful.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v was successful.
# 3 compiles, 0 failed with no errors.
restart -f
# Loading work.keboda_testbench
# Loading work.keboda_sar
# Loading work.keboda_ana_adc
# Warning in wave window restart: (vish-4014) No objects found matching '/keboda_testbench/CK'. 
# Warning in wave window restart: (vish-4014) No objects found matching '/keboda_testbench/RSTB'. 
run -all
# Compile of keboda_testbench.sv was successful.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v was successful.
# 3 compiles, 0 failed with no errors.
restart -f
# Loading work.keboda_testbench
# Loading work.keboda_sar
# Loading work.keboda_ana_adc
# Warning in wave window restart: (vish-4014) No objects found matching '/keboda_testbench/EOC'. 
# Warning in wave window restart: (vish-4014) No objects found matching '/keboda_testbench/lilipipo'. 
run -all
# Compile of keboda_testbench.sv was successful.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v was successful.
# 3 compiles, 0 failed with no errors.
restart -f
# Loading work.keboda_testbench
# Loading work.keboda_sar
# Loading work.keboda_ana_adc
run -all
# Compile of keboda_testbench.sv was successful.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v was successful.
# 3 compiles, 0 failed with no errors.
restart -f
# Loading work.keboda_testbench
# Loading work.keboda_sar
# Loading work.keboda_ana_adc
# ** Error: (vsim-3063) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(62): Port 'COMP' not found in the connected module (4th connection).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/SAR File: D:/Logiciels/EDA/intelFPGA/17.0/keboda_sar.v
# Compile of keboda_testbench.sv was successful.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v was successful.
# 3 compiles, 0 failed with no errors.
restart -f
# No Design Loaded!
restart -f
# No Design Loaded!
vsim work.keboda_testbench
# vsim work.keboda_testbench 
# Start time: 17:29:19 on Nov 26,2017
# Loading sv_std.std
# Loading work.keboda_testbench
# Loading work.keboda_sar
# Loading work.keboda_ana_adc
add wave -position insertpoint  \
sim:/keboda_testbench/A \
sim:/keboda_testbench/DATA_HOLD \
sim:/keboda_testbench/REF \
sim:/keboda_testbench/clk \
sim:/keboda_testbench/rstb \
sim:/keboda_testbench/eoc \
sim:/keboda_testbench/START_CONV \
sim:/keboda_testbench/MSB_therm_code \
sim:/keboda_testbench/LSB_code \
sim:/keboda_testbench/ON \
sim:/keboda_testbench/X
run -all
run -all
run -all
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# Compile of keboda_testbench.sv was successful.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v was successful.
# 15 compiles, 0 failed with no errors.
restart -f
# Loading work.keboda_testbench
# Loading work.keboda_sar
# Loading work.keboda_ana_adc
run -all
# ** Note: $finish    : D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(56)
#    Time: 8000380 us  Iteration: 0  Instance: /keboda_testbench
# 1
# Break in Module keboda_testbench at D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv line 56
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# Compile of keboda_testbench.sv was successful.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v was successful.
# 15 compiles, 0 failed with no errors.
restart -f
# Loading work.keboda_testbench
# Loading work.keboda_sar
# Loading work.keboda_ana_adc
# ** Error: (vsim-3063) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(64): Port 'START_CONV' not found in the connected module (3rd connection).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/SAR File: D:/Logiciels/EDA/intelFPGA/17.0/keboda_sar.v
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# Compile of keboda_testbench.sv was successful.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v was successful.
# 15 compiles, 0 failed with no errors.
restart -f
# No Design Loaded!
vsim work.keboda_testbench
# vsim work.keboda_testbench 
# Start time: 17:29:19 on Nov 26,2017
# Loading sv_std.std
# Loading work.keboda_testbench
# Loading work.keboda_sar
# Loading work.keboda_ana_adc
# Warning in wave window restart: (vish-4014) No objects found matching '/keboda_testbench/START_CONV'. 
add wave -position insertpoint  \
sim:/keboda_testbench/A \
sim:/keboda_testbench/DATA_HOLD \
sim:/keboda_testbench/REF \
sim:/keboda_testbench/clk \
sim:/keboda_testbench/rstb \
sim:/keboda_testbench/eoc \
sim:/keboda_testbench/enable_sar \
sim:/keboda_testbench/MSB_therm_code \
sim:/keboda_testbench/LSB_code \
sim:/keboda_testbench/ON \
sim:/keboda_testbench/X
run -all
run -all
run -all
# ** Note: $finish    : D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(56)
#    Time: 8000380 us  Iteration: 0  Instance: /keboda_testbench
# 1
# Break in Module keboda_testbench at D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv line 56
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# Compile of keboda_testbench.sv was successful.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v failed with 1 errors.
# 15 compiles, 1 failed with 1 error.
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# Compile of keboda_testbench.sv was successful.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v was successful.
# 15 compiles, 0 failed with no errors.
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# Compile of keboda_testbench.sv was successful.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v failed with 2 errors.
# 15 compiles, 1 failed with 2 errors.
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# Compile of keboda_testbench.sv was successful.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v was successful.
# 15 compiles, 0 failed with no errors.
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# Compile of keboda_testbench.sv failed with 1 errors.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v was successful.
# 15 compiles, 1 failed with 1 error.
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# Compile of keboda_testbench.sv was successful.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v was successful.
# 15 compiles, 0 failed with no errors.
restart -f
# Loading work.keboda_testbench
# Loading work.keboda_sar
# Loading work.keboda_ana_adc
# Warning in wave window restart: (vish-4014) No objects found matching '/keboda_testbench/MSB_therm_code'. 
# Warning in wave window restart: (vish-4014) No objects found matching '/keboda_testbench/LSB_code'. 
add wave -position insertpoint  \
sim:/keboda_testbench/A \
sim:/keboda_testbench/DATA_HOLD \
sim:/keboda_testbench/REF \
sim:/keboda_testbench/clk \
sim:/keboda_testbench/rstb \
sim:/keboda_testbench/eoc \
sim:/keboda_testbench/enable_sar \
sim:/keboda_testbench/msb_therm \
sim:/keboda_testbench/lsb_binary \
sim:/keboda_testbench/ON \
sim:/keboda_testbench/X
run -all
# ** Note: $finish    : D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(56)
#    Time: 8000380 us  Iteration: 0  Instance: /keboda_testbench
# 1
# Break in Module keboda_testbench at D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv line 56
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# Compile of keboda_testbench.sv was successful.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v was successful.
# 15 compiles, 0 failed with no errors.
restart -f
# Loading work.keboda_testbench
# Loading work.keboda_sar
# Loading work.keboda_ana_adc
run -all
# ** Note: $finish    : D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(56)
#    Time: 8000380 us  Iteration: 0  Instance: /keboda_testbench
# 1
# Break in Module keboda_testbench at D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv line 56
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# Compile of keboda_testbench.sv was successful.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v was successful.
# 15 compiles, 0 failed with no errors.
restart -f
# Loading work.keboda_testbench
# Loading work.keboda_sar
# Loading work.keboda_ana_adc
# Warning in wave window restart: (vish-4014) No objects found matching '/keboda_testbench/DATA_HOLD'. 
add wave -position insertpoint  \
sim:/keboda_testbench/A \
sim:/keboda_testbench/data_conv \
sim:/keboda_testbench/REF \
sim:/keboda_testbench/clk \
sim:/keboda_testbench/rstb \
sim:/keboda_testbench/eoc \
sim:/keboda_testbench/enable_sar \
sim:/keboda_testbench/msb_therm \
sim:/keboda_testbench/lsb_binary \
sim:/keboda_testbench/ON \
sim:/keboda_testbench/X
run -all
# ** Note: $finish    : D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(56)
#    Time: 8000380 us  Iteration: 0  Instance: /keboda_testbench
# 1
# Break in Module keboda_testbench at D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv line 56
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# Compile of keboda_testbench.sv was successful.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v was successful.
# Compile of keboda_sequencer.v was successful.
# 16 compiles, 0 failed with no errors.
restart -f
# Loading work.keboda_testbench
# Loading work.keboda_sar
# Loading work.keboda_ana_adc
run -all
# ** Note: $finish    : D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(61)
#    Time: 8000380 us  Iteration: 0  Instance: /keboda_testbench
# 1
# Break in Module keboda_testbench at D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv line 61
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# Compile of keboda_testbench.sv was successful.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v was successful.
# Compile of keboda_sequencer.v was successful.
# 16 compiles, 0 failed with no errors.
restart -f
# Loading work.keboda_testbench
# Loading work.keboda_sar
# Loading work.keboda_ana_adc
# Loading work.channel_selector
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(105): [PCDPC] - Port size (8) does not match connection size (1) for port 'out'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(105): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(105): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(105): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(105): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(105): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(105): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(44): Variable '/keboda_testbench/ON', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(79).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench File: D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv
# Warning in wave window restart: (vish-4014) No objects found matching '/keboda_testbench/clk'. 
add wave -position insertpoint  \
sim:/keboda_testbench/A \
sim:/keboda_testbench/data_conv \
sim:/keboda_testbench/REF \
sim:/keboda_testbench/clk_1us \
sim:/keboda_testbench/rstb \
sim:/keboda_testbench/eoc \
sim:/keboda_testbench/enable_sar \
sim:/keboda_testbench/msb_therm \
sim:/keboda_testbench/lsb_binary \
sim:/keboda_testbench/ON \
sim:/keboda_testbench/clk_1ms \
sim:/keboda_testbench/en_sequencer \
sim:/keboda_testbench/testmode \
sim:/keboda_testbench/adc_pd \
sim:/keboda_testbench/X \
sim:/keboda_testbench/mux_channel \
sim:/keboda_testbench/in0 \
sim:/keboda_testbench/in1 \
sim:/keboda_testbench/in2 \
sim:/keboda_testbench/in3 \
sim:/keboda_testbench/in4 \
sim:/keboda_testbench/select
run -all
# ** Note: $finish    : D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(76)
#    Time: 8000380 us  Iteration: 0  Instance: /keboda_testbench
# 1
# Break in Module keboda_testbench at D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv line 76
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# Compile of keboda_testbench.sv was successful.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v was successful.
# Compile of keboda_sequencer.v was successful.
# 16 compiles, 0 failed with no errors.
restart -f
# Loading work.keboda_testbench
# Loading work.keboda_sar
# Loading work.keboda_ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(118): [PCDPC] - Port size (8) does not match connection size (1) for port 'out'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(118): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(118): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(118): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(118): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(118): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(118): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(13).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(26).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(48): Variable '/keboda_testbench/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench File: D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(44): Variable '/keboda_testbench/ON', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(92).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench File: D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv
add wave -position insertpoint  \
sim:/keboda_testbench/A \
sim:/keboda_testbench/data_conv \
sim:/keboda_testbench/REF \
sim:/keboda_testbench/clk_1us \
sim:/keboda_testbench/rstb \
sim:/keboda_testbench/eoc \
sim:/keboda_testbench/enable_sar \
sim:/keboda_testbench/msb_therm \
sim:/keboda_testbench/lsb_binary \
sim:/keboda_testbench/ON \
sim:/keboda_testbench/clk_1ms \
sim:/keboda_testbench/en_sequencer \
sim:/keboda_testbench/testmode \
sim:/keboda_testbench/adc_pd \
sim:/keboda_testbench/X \
sim:/keboda_testbench/mux_channel \
sim:/keboda_testbench/in0 \
sim:/keboda_testbench/in1 \
sim:/keboda_testbench/in2 \
sim:/keboda_testbench/in3 \
sim:/keboda_testbench/in4 \
sim:/keboda_testbench/select \
sim:/keboda_testbench/adc_data \
sim:/keboda_testbench/range_mux_ctrl \
sim:/keboda_testbench/ch1_range1_data \
sim:/keboda_testbench/ch1_range2_data \
sim:/keboda_testbench/ch1_range3_data \
sim:/keboda_testbench/ch2_data \
sim:/keboda_testbench/ch3_data \
sim:/keboda_testbench/ch4_data \
sim:/keboda_testbench/ch5_data \
sim:/keboda_testbench/test_mux_data_conv \
sim:/keboda_testbench/acq_cycle_done
run -all
# ** Note: $finish    : D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(88)
#    Time: 4186 us  Iteration: 2  Instance: /keboda_testbench
# 1
# Break in Module keboda_testbench at D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv line 88
add wave -position insertpoint  \
sim:/keboda_testbench/sequencer/channel
run -all
restart -f
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(118): [PCDPC] - Port size (8) does not match connection size (1) for port 'out'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(118): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(118): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(118): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(118): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(118): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(118): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(13).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(26).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(48): Variable '/keboda_testbench/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench File: D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(44): Variable '/keboda_testbench/ON', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(92).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench File: D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# Compile of keboda_testbench.sv was successful.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v was successful.
# Compile of keboda_sequencer.v was successful.
# 16 compiles, 0 failed with no errors.
restart -f
# Loading work.keboda_testbench
# Loading work.keboda_sar
# Loading work.keboda_ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(107): [PCDPC] - Port size (8) does not match connection size (1) for port 'REF'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/keboda_ana_adc.v(8).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/ana_adc File: D:/Logiciels/EDA/intelFPGA/17.0/keboda_ana_adc.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(118): [PCDPC] - Port size (8) does not match connection size (1) for port 'out'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(118): [PCDPC] - Port size (8) does not match connection size (1) for port 'in0'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(118): [PCDPC] - Port size (8) does not match connection size (1) for port 'in1'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(118): [PCDPC] - Port size (8) does not match connection size (1) for port 'in2'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(118): [PCDPC] - Port size (8) does not match connection size (1) for port 'in3'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(118): [PCDPC] - Port size (8) does not match connection size (1) for port 'in4'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(118): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(13).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(26).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(48): Variable '/keboda_testbench/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(130).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench File: D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(44): Variable '/keboda_testbench/ON', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(92).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench File: D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv
add wave -position insertpoint  \
sim:/keboda_testbench/sequencer/channel_mux_ctrl
run -all
# ** Note: $finish    : D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(88)
#    Time: 4186 us  Iteration: 2  Instance: /keboda_testbench
# 1
# Break in Module keboda_testbench at D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv line 88
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# Compile of keboda_testbench.sv was successful.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v was successful.
# Compile of keboda_sequencer.v was successful.
# 16 compiles, 0 failed with no errors.
restart -f
# Loading work.keboda_testbench
# Loading work.keboda_sar
# Loading work.keboda_ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(115): [PCDPC] - Port size (8) does not match connection size (1) for port 'REF'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/keboda_ana_adc.v(8).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/ana_adc File: D:/Logiciels/EDA/intelFPGA/17.0/keboda_ana_adc.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(126): [PCDPC] - Port size (8) does not match connection size (1) for port 'out'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(126): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(138): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(13).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(138): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(138): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(138): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(138): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(138): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(138): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(138): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(138): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(138): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(138): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(26).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(50): Variable '/keboda_testbench/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(138).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench File: D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(46): Variable '/keboda_testbench/ON', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(100).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench File: D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv
run -all
# ** Note: $finish    : D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(96)
#    Time: 4186 us  Iteration: 2  Instance: /keboda_testbench
# 1
# Break in Module keboda_testbench at D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv line 96
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# Compile of keboda_testbench.sv failed with 1 errors.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v was successful.
# Compile of keboda_sequencer.v was successful.
# 16 compiles, 1 failed with 1 error.
# Compile of test.v was successful.
# Compile of sar01.v was successful.
# Compile of sar.v was successful.
# Compile of ana_adc.v was successful.
# Compile of bench_sar.v was successful.
# Compile of toto.sv was successful.
# Compile of sequencer.v was successful.
# Compile of mux_channel.v was successful with warnings.
# Compile of mux_tb.v was successful.
# Compile of channel_selector.v was successful.
# Compile of sar_bis.v was successful.
# Compile of edge_detect.v was successful.
# Compile of keboda_testbench.sv was successful.
# Compile of keboda_ana_adc.v was successful.
# Compile of keboda_sar.v was successful.
# Compile of keboda_sequencer.v was successful.
# 16 compiles, 0 failed with no errors.
restart -f
# Loading work.keboda_testbench
# Loading work.keboda_sar
# Loading work.keboda_ana_adc
# Loading work.channel_selector
# Loading work.sequencer
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(126): [PCDPC] - Port size (8) does not match connection size (1) for port 'out'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(126): [PCDPC] - Port size (3) does not match connection size (1) for port 'select'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v(3).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/channel_selector File: D:/Logiciels/EDA/intelFPGA/17.0/channel_selector.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(138): [PCDPC] - Port size (8) does not match connection size (1) for port 'adc_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(13).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(138): [PCDPC] - Port size (3) does not match connection size (1) for port 'channel_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(17).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(138): [PCDPC] - Port size (2) does not match connection size (1) for port 'range_mux_ctrl'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(18).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(138): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range1_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(19).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(138): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(20).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(138): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch1_range3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(21).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(138): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch2_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(22).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(138): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch3_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(23).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(138): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch4_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(24).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(138): [PCDPC] - Port size (8) does not match connection size (1) for port 'ch5_data'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(25).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3015) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(138): [PCDPC] - Port size (8) does not match connection size (1) for port 'test_mux_data_conv'. The port definition is at: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v(26).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench/sequencer File: D:/Logiciels/EDA/intelFPGA/17.0/sequencer.v
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(50): Variable '/keboda_testbench/adc_pd', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(138).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench File: D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv
# ** Warning: (vsim-3839) D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(46): Variable '/keboda_testbench/ON', driven via a port connection, is multiply driven. See D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(100).
#    Time: 0 ps  Iteration: 0  Instance: /keboda_testbench File: D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv
run -all
# ** Note: $finish    : D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv(96)
#    Time: 4186 us  Iteration: 2  Instance: /keboda_testbench
# 1
# Break in Module keboda_testbench at D:/Logiciels/EDA/intelFPGA/17.0/keboda_testbench.sv line 96
