# Reading D:/Logiciels/EDA/intelFPGA/17.0/modelsim_ase/tcl/vsim/pref.tcl
vsim work.first_counter_tb
# vsim work.first_counter_tb 
# Start time: 18:15:54 on Jul 23,2017
# Loading work.first_counter_tb
# Loading work.first_counter
add wave -position insertpoint  \
sim:/first_counter_tb/clock \
sim:/first_counter_tb/reset \
sim:/first_counter_tb/enable \
sim:/first_counter_tb/counter_out
run
# time	 clk reset enable counter
# 0	 1   0     0      xxxx
# 5	 0   1     0      xxxx
# 10	 1   1     0      xxxx
# 11	 1   1     0      0000
# 15	 0   0     0      0000
# 20	 1   0     0      0000
# 25	 0   0     1      0000
# 30	 1   0     1      0000
# 31	 1   0     1      0001
# 35	 0   0     1      0001
# 40	 1   0     1      0001
# 41	 1   0     1      0010
# 45	 0   0     1      0010
# 50	 1   0     1      0010
# 51	 1   0     1      0011
# 55	 0   0     1      0011
# 60	 1   0     1      0011
# 61	 1   0     1      0100
# 65	 0   0     1      0100
# 70	 1   0     1      0100
# 71	 1   0     1      0101
# 75	 0   0     1      0101
# 80	 1   0     1      0101
# 81	 1   0     1      0110
# 85	 0   0     1      0110
# 90	 1   0     1      0110
# 91	 1   0     1      0111
# 95	 0   0     1      0111
quit -sim
# End time: 18:16:45 on Jul 23,2017, Elapsed time: 0:00:51
# Errors: 0, Warnings: 0
# Loading project Dev
quit
