#!/bin/sh
# This file was generated by:
#
#	Techgen -trans version 7.1 Linux 32 bit - (Wed Jul 23 07:38:37 PDT 2008)	Thu Sep 18 13:16:28 2008
#
#------------------------------------------
# BEGIN: Initializations
#
# net file
#
NETFILE="net_1"
#
#
# resistive interconnect variables.  Some of this information is from
# the process file:
#       RINTERPROCESS - process layers for which R will be extracted
#       RINTERHEIGHT - height (thickness) of RINTERPROCESS layers
#       RINTERFILL - grow/shrink amount for RINTERPROCESS layers
#       RINTERBIAS - bias of RINTERPROCESS layers
#       RINTERRES     - sheet resistance of process layers
#       RINTERRANGE  - separation range for 2d capacitance extraction
#       RINTERSEP     - maximum separation for 2d capacitance extraction
#       RTHRESHSEP    - 'infinity' threshhold.  Conductors separated
#                       by this distance are treated as if isolated
# and some from extraction:
#       RINTERCONNECT - extraction layers which correspond to RINTERPROCESS 
#                       layers
# and some from the user
#       RNAMEPREFIX   - resistor name prefixes (these will appear in the dspf)
#       RPROCESSTC    -process layer temperature coefficient TC1,TC2 
#
# The resistive interconnect variables correspond by position, so they must
# all have the same number of elements.  They must also be in top-down process
# order.
#
RINTERPROCESS="mt6 mt5 mt4 mt3 mt2 mt1 poly"
RINTERHEIGHT="0.99 0.6 0.53 0.53 0.53 0.53 0.2"
RINTERFILL="0.679 0.449 0.449 0.449 0.449 0.449 0.389"
RINTERBIAS="0 0 0 0 0 0 0"
RINTERRES="0.1 0.1 0.1 0.1 0.1 0.1 7.5"
RINTERRANGE="3.68 3 3 3 3 3 3"
RINTERSEP="3.68 3 3 3 3 3 3"
RTHRESHSEP="3.681 3.001 3.001 3.001 3.001 3.001 3.001"
RINTERCONNECT="M6term M5term M4term M3term M2term M1term POLYterm"
RMODELNAME="mt6 mt5 mt4 mt3 mt2 mt1 poly"
RNAMEPREFIX="a b c d e f g"
RPROCESSTC="- - - - - - -"
#
# RTEXT - contains the text layers which appeared in the extraction
#         and apply to the RINTERCONNECT layers. Each entry must have the form:
#
#               text-layer-name,inter-connect-layer-name
#
#         interconnect-layer-names must appear in the list specified for 
#         RINTERCONNECT
# RTEXTI- contains text layers and corresponding indices into the RINTERCONNECT
#         list. Indices are determined from right to left.  The rightmost
#         RINTERCONNECT layer has an index of 1.
# NRTEXT - text layers attaching to non-resitive layers.
#
RTEXT="Metal6_text,M6term Metal6_pintext,M6term Metal5_text,M5term Metal5_pintext,M5term Metal4_text,M4term Metal4_pintext,M4term Metal3_text,M3term Metal3_pintext,M3term Metal2_text,M2term Metal2_pintext,M2term Metal1_text,M1term Metal1_pintext,M1term"
RTEXTI="Metal6_text,7 Metal6_pintext,7 Metal5_text,6 Metal5_pintext,6 Metal4_text,5 Metal4_pintext,5 Metal3_text,4 Metal3_pintext,4 Metal2_text,3 Metal2_pintext,3 Metal1_text,2 Metal1_pintext,2"
NRTEXT=
#
# MARKERLAYERS - non-extracted LVS layers.
MARKERLAYERS=
#
# RVIAS - contains the via layers and the interconnect layers to which they
#         apply. Each entry must have the form:
#
#               via-layer-name,interconnect-layer1,interconnect-layer2
#
#         interconnect layers must appear in TINTEREXT
# SRVIAS - list of via names
# RVIAR - contains via resistance.  A dash indicates no resistance.
#         this list must correspond to the RVIAS list
# DAVIAS - contains vias for which the array_vias feature should be disabled.
# ARRAYVIASPACING - contains via,value pairs for the array_vias feature.
# VIAUNITAREA - contains via,value pairs for the via_unit_area feature.
# VIATC - contains via,value1,value2  pairs for the TC1,TC2 feature.
#
BVIAS=
RVIAS="Via5,M6term,M5term Via4,M5term,M4term Via3,M4term,M3term Via2NoCapInd,M3term,M2term Via2Cap,M3term,CapMetal Via1,M2term,M1term INDterm1Cont,M2term,INDterm1 INDterm2Cont,M2term,INDterm2 POLYcont,M1term,POLYterm PSDcont,M1term,PSDterm NSDcont,M1term,NSDterm JVARterm_PSDterm_ovia,JVARterm,PSDterm JVARanode_JVARterm_ovia,JVARanode,JVARterm"
SRVIAS="Via5 Via4 Via3 Via2NoCapInd Via2Cap Via1 INDterm1Cont INDterm2Cont POLYcont PSDcont NSDcont JVARterm_PSDterm_ovia JVARanode_JVARterm_ovia"
RSOFTVIAS=
RVIAR="2 2 2 2 2 2 - - 5 7 7 - -"
DAVIAS=
ARRAYVIASPACING=
VIAUNITAREA=
VIATC="- - - - - - - - - - - - -"
VIAUAVAL="- - - - - - - - - - - - -"
#
# REXVIASI - Vias which connect one or more resistive layers and corresponding
#            indices into the RINTERCONNECT list.  Indices are determined from
#            right to left.  The rightmost RINTERCONNECT layer's index is 1.
#
REXVIASI="INDterm1Cont,3 INDterm2Cont,3 NSDcont,2,t POLYcont,1,2,t PSDcont,2,t Via1,2,3,t Via2Cap,4,t Via2NoCapInd,3,4,t Via3,4,5,t Via4,5,6,t Via5,6,7,t"
# NEBULAVIAS - Vias which take part in nebula cap extraction and the
#              corresponding indices into the TINTEREXT list.
NEBULAVIAS="Via5,8,9 Via4,7,8 Via3,6,7 Via2NoCapInd,5,6 Via1,4,5 POLYcont,3,4 PSDcont,2,4 NSDcont,2,4"
# PGDBVIAS - Vias which take part in rcx2pgdb and the
#              corresponding indices into the RINTERPROCESS list.
PGDBVIAS="Via5:1:2 Via4:2:3 Via3:3:4 Via2NoCapInd:4:5 Via1:5:6 POLYcont:6:7 PSDcont:6 NSDcont:6"
#
# ALLWIRES - list of connectable layers
#
ALLWIRES="CapMetal INDterm1 INDterm2 JVARanode JVARterm M1term M2term M3term M4term M5term M6term NSDterm POLYterm PSDterm"
#
# NRINTERCONNECT - connectable layers which are non-resistive
# NRINTERPROCESS - non-resistive connectable layers grouped according to common process mapping layers
#
NRINTERCONNECT="CapMetal INDterm1 INDterm2 JVARanode JVARterm NSDterm PSDterm"
NRINTERPROCESS="CapMetal INDterm1 INDterm2 JVARanode JVARterm PSDterm,NSDterm"
#
# RRVIAS - vias which connect a pair of resistive layers
# NRVIAS - vias which connect one resistive and one non-resistive layer and
#          the non-resistive layer.
# NNVIASI - vias which connect a pair of non-resistive layers and corresponding
#          indices into the NRINTERPROCESS list.  Indices are determined from
#          left to right.  The leftmost NRINTERPROCESS layer's index is 1
# NNSOFTVIASI - vias which sconnect a pair of non-resistive layers and
#          corresponding indices into the NRINTERPROCESS list.
#
RRVIAS="POLYcont,M1term,POLYterm Via1,M2term,M1term Via2NoCapInd,M3term,M2term Via3,M4term,M3term Via4,M5term,M4term Via5,M6term,M5term"
NRVIAS="INDterm1Cont,INDterm1 INDterm2Cont,INDterm2 NSDcont,NSDterm PSDcont,PSDterm Via2Cap,CapMetal"
NNVIASI="JVARanode_JVARterm_ovia,4,5 JVARterm_PSDterm_ovia,5,6"
NNSOFTVIASI=
#
# ACRVIAS - vias for which contact resistance is considered under ?addExplicitVias
# ACRMODEL - model names corresponding to ACRVIAS
# ACRPREFIX - prefices corresponding to ACRVIAS
# ACRVAL - resistance values corresponding to ACRVIAS
# TACRVIAS - vias for which contact resistance is always considered
ACRVIAS="Via5 Via4 Via3 Via2NoCapInd Via2Cap Via1 POLYcont PSDcont NSDcont"
ACRMODEL="Via5 Via4 Via3 Via2NoCapInd Via2Cap Via1 POLYcont PSDcont NSDcont"
ACRPREFIX="h i j k l m n o p"
ACRVAL="2 2 2 2 2 2 5 7 7"
TACRVIAS=
#
# TINTEREXT - the set of interconnect layers which correspond to the layers 
#             specified in the process file
#
TINTEREXT="M6term M5term M4term M3term M2term M1term POLYterm PSDterm,NSDterm Pwell,ISOPWELL,PSUB,NBVIA,Nburied,NWELLterm"
#
# SPROCESS - list of layers which are defined as substrate in the process file
#	     (must be in top-down order)
# SINTEREXT -list of extraction layers which correspond to the ${SPROCESS}
#            layers.  The number of elements in the SPROCESS and SINTEREXT
#            lists must be the same
#
SPROCESS="diff sub"
SINTEREXT="PSDterm,NSDterm Pwell,ISOPWELL,PSUB,NBVIA,Nburied,NWELLterm"
#
# NRPROCESS - non resistive process layers (other than substrate)
# NRINTEREXT -non resistive extraction layers (other than substrate)
# NRINTERRANGE -non resistive separation range for 2d capacitance extraction
# NRINTERSEP -non resistive maximum separation for 2d capacitance extraction
# NRTHRESHSEP-non resistive 'infinity' threshhold.  Conductors separated
#             by this distance are treated as if isolated
#
NRPROCESS=
NRINTEREXT=
NRINTERRANGE=
NRINTERSEP=
NRTHRESHSEP=
#
# TPROCESS - list of layers defined in the process file (must be in top-down
#            order)
# PROCESSGROWAMT-process layer grow amount (must be positive & less than 1/2
#            the minimum design rule separation for the layer)
# PROCESSMINWIDTH-process layer minimum width
# PROCESSMINWIDTH-process layer minimum width
# PROCESSMAXWIDTH-process layer maximum width
# PROCESSEROSION-process layer erosion specification
# PROCESSTOPHEIGHT-process layer top-height specification (top height including
#         metal thickness,relative to deepmost substrate assuming all metal lyrs
#         are present; max possible height in case of non-planar dielectrics
# PROCESSTHICKNESS-process layer thickness (similar to RINTERHEIGHT, covers all proc lyrs)
# TOTALHEIGHT-height of non-substrate process layers and dielectrics
#
TPROCESS="mt6 mt5 mt4 mt3 mt2 mt1 poly diff sub"
PROCESSGROWAMT="- - - - - - - - -"
PROCESSMINWIDTH="0.44 0.3 0.3 0.3 0.3 0.3 0.18 - -"
PROCESSMAXWIDTH="3.52 3 3 3 3 3 1.8 - -"
PROCESSEROSION="- - - - - - - - -"
LOADINGEFFECT="- - - - - - - - -"
PROCESSTOPHEIGHT="8.76 6.97 5.57 4.24 2.91 1.58 0.55 0.35 0.35"
PROCESSTHICKNESS="0.99 0.6 0.53 0.53 0.53 0.53 0.2 0.005 0.35"
TOTALHEIGHT="8.41"
#
# STMPLAYERS - extraction layers which are used to stamp the layers in STMPTERMS
# STMPTERMS - extraction layers which get stamped with net info
#          each entry must have the form terminal-layer,stamping-layer
# STMPTYPES - either single (1) or multi (2) stamp type
# STMPOELAYERS - other ext_layers
#
STMPLAYERS="Pwell ISOPWELL PSUB NBVIA Nburied NWELLterm"
STMPTYPES="2 2 2 2 2 2"
STMPTERMS="NWVIA,NSDterm NWELLterm,NWVIA PWVIA,PSDterm Pwell,PWVIA PWNBVIA,PSDterm ISOPWELL,PWNBVIA SUBVIA,PSDterm PSUB,SUBVIA NBVIA,NWELLterm Nburied,NBVIA"
STMPOELAYERS="PWVIA,PWNBVIA,SUBVIA,NWVIA PWVIA,PWNBVIA,SUBVIA,NWVIA PWVIA,PWNBVIA,SUBVIA,NWVIA PWVIA,PWNBVIA,SUBVIA,NWVIA PWVIA,PWNBVIA,SUBVIA,NWVIA PWVIA,PWNBVIA,SUBVIA,NWVIA"
#
# 3d capacitance variables. Capacitance will be modeled for pairs of layers
# specified here.
#
# PROCESSCOMB - list of pairs, each entry must have the form: layer1,layer2
#	        and the members of each pair must be specified in top down
#	        order.  This information is extracted from the process file
# PROCESSCOMBRANGE - separation range between pairs specified in the PROCESSCOMB list.
# PROCESSCOMBSEP - separation between pairs specified in the PROCESSCOMB list.
#	        This information is also extracted from the process file
#
PROCESSCOMB="poly,mt1 poly,mt2 mt1,mt2 mt1,mt3 mt2,mt3 mt2,mt4 mt3,mt4 mt3,mt5 mt4,mt5 mt4,mt6 mt5,mt6"
PROCESSCOMBRANGE="0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9"
PROCESSCOMBSEP="3 3 3 3 3 3 3 3 3 3 3"
#
# VARIATIONPARAMETERS - variation file contents for simulating process parameter variations. 
#
VARIATIONPARAM=
#
# Gate specifications. (See capgen -p[a])
#
# PGATE - process gate layers
# EXTGATE - extraction gate layers.  MOS and LDD device layers specified
#           in the process to extraction mapping file
#
PGATE="poly"
EXTGATE=""
#
# Gate capacitance blocking
#
# POLYGATES - gate,poly,diff layer triplets specified in capgen -p options
#
POLYGATES="allGate,poly,diff"
#
# Cap mask layer specifications. (See capgen -c)
#
# EXTMASK - extraction mask layers.  These layers are from the -c file
#           and act as filters to avoid counting again capacitance which
#           has already been included in the various canonical devices
#           Note: number of EXTMASK + EXTGATE + TPROCESS layers may not
#           exceed 16
#
EXTMASK=
#
# PAD specifications
#
PADDEV=
PADTERM=
#
# MOSFET Device specifications
#
MOSDEV="PMOSCAP_MOS_595 NMOSCAP_MOS_619 ISONMOSCAP_MOS_643 NMOS_MOS_696 ISONMOS_MOS_720 NMOSHV_MOS_744 ISONMOSHV_MOS_768 NMOSRF_MOS_792 ISONMOSRF_MOS_816 PMOS_MOS_840 PMOSHV_MOS_864 PMOSRF_MOS_888"
MOSSRCDRN="PSDterm NSDterm NSDterm NSDterm NSDterm NSDterm NSDterm NSDterm NSDterm PSDterm PSDterm PSDterm"
MOSGATE="POLYterm POLYterm POLYterm POLYterm POLYterm POLYterm POLYterm POLYterm POLYterm POLYterm POLYterm POLYterm"
MOSSUB="NWELLterm PSUB ISOPWELL PSUB ISOPWELL PSUB ISOPWELL PSUB ISOPWELL NWELLterm NWELLterm NWELLterm"
MOSTYPE="pmoscap nmoscap nmoscap_av2 nmos nmos_av2 nmoshv nmoshv_av2 nmosrf nmosrf_av2 pmos pmoshv pmosrf"
MOSMODEL="pmoscap nmoscap nmoscap nmos nmos nmoshv nmoshv nmosrf nmosrf pmos pmoshv pmosrf"
MOSDF2MODEL="pmoscap#20ivpcell#20gpdk180 nmoscap#20ivpcell#20gpdk180 nmoscap#20ivpcell#20gpdk180 nmos#20ivpcell#20gpdk180 nmos#20ivpcell#20gpdk180 nmoshv#20ivpcell#20gpdk180 nmoshv#20ivpcell#20gpdk180 nmosrf#20ivpcell#20gpdk180 nmosrf#20ivpcell#20gpdk180 pmos#20ivpcell#20gpdk180 pmoshv#20ivpcell#20gpdk180 pmosrf#20ivpcell#20gpdk180"
MOSLDDDIFFCONTS=
#
# LDD Device specifications
#
LDDDEV=
LDDDRN=
LDDSRC=
LDDGATE=
LDDSUB=
LDDTYPE=
LDDMODEL=
LDDDF2MODEL=
#
# MOS model file (for ADVGEN)
#
MOSMODELFILE=
#
# BJT Device specifications
#
BJTDEV="VPNP_BJT_672 PNP_BJT_680 NPN_BJT_688"
BJTCOL="PSUB Pwell Nburied"
BJTBASE="NWELLterm NWELLterm Pwell"
BJTEMIT="PSDterm PSDterm NSDterm"
BJTSUB="- - -"
BJTTYPE="vpnp pnp npn"
BJTMODEL="vpnp pnp npn"
BJTDF2MODEL="vpnp#20ivpcell#20gpdk180 pnp#20ivpcell#20gpdk180 npn#20ivpcell#20gpdk180"
BJTMF=
#
# RESISTOR Device specifications
#
RESDEV="POLYRES_RES_321 POLYHRES_RES_342 NSDRES_RES_365 ISONSDRES_RES_388 PSDRES_RES_411 NWELLRES_RES_432 M1res_RES_453 M2res_RES_474 M3res_RES_495 M4res_RES_516 M5res_RES_537 M6res_RES_558"
RESTERM="POLYterm POLYterm NSDterm NSDterm PSDterm NWELLterm M1term M2term M3term M4term M5term M6term"
RESSUB="- - PSUB ISOPWELL NWELLterm - - - - - - -"
RESTYPE="polyres polyhres nplusres nplusres_av2 pplusres nwellres m1res m2res m3res m4res m5res m6res"
RESMODEL="polyres polyhres nplusres nplusres pplusres nwellres m1res m2res m3res m4res m5res m6res"
RESDF2MODEL="polyres#20ivpcell#20gpdk180 polyhres#20ivpcell#20gpdk180 nplusres#20ivpcell#20gpdk180 nplusres#20ivpcell#20gpdk180 pplusres#20ivpcell#20gpdk180 nwellres#20ivpcell#20gpdk180 m1res#20ivpcell#20gpdk180 m2res#20ivpcell#20gpdk180 m3res#20ivpcell#20gpdk180 m4res#20ivpcell#20gpdk180 m5res#20ivpcell#20gpdk180 m6res#20ivpcell#20gpdk180"
RESPARAM="1 1 1 1 1 1 1 1 1 1 1 1"
#
# RES model file (for ADVGEN)
#
RESMODELFILE=
#
# CAP Device specifications
#
CAPDEV="MIMCAP_CAP_581"
CAPTERM1="CapMetal"
CAPTERM2="M2term"
CAPACONST="-"
CAPSUB="-"
CAPTYPE="mimcap"
CAPMODEL="mimcap"
CAPDF2MODEL="mimcap#20ivpcell#20gpdk180"
CAPPARAM="1e-15"
CAPMF=
#
# DIODE Device specifications
#
DIODEV="NDIODE_DIODE_910 PDIODE_DIODE_917 JVARNF_DIODE_926 JVARW40_DIODE_935"
DIOTERM1="PSUB PSDterm JVARanode JVARanode"
DIOTERM2="NSDterm NWELLterm NWELLterm NWELLterm"
DIOSUB="- - PSUB PSUB"
DIOTYPE="ndio pdio xjvar_w40 xjvar_nf36"
DIOMODEL="ndio pdio xjvar_w40 xjvar_nf36"
DIODF2MODEL="ndio#20ivpcell#20gpdk180 pdio#20ivpcell#20gpdk180 xjvar_w40#20ivpcell#20gpdk180 xjvar_nf36#20ivpcell#20gpdk180"
DIOPARAM="1 1 1 1"
DIOMF=
#
# GENERIC Device specifications
#
GENDEV="INDUCTOR_Device_665"
GENTERMS="INDterm1,INDterm2"
GENMOS=
GENMOSSRC=
GENMOSDRN=
GENMOSGATE=
GENMOSSUB=
GENMOSSUB2=
GENMOSTYPE=
GENCDEV=
GENCTERMS=
GENCCONST=
GENRDEV=
GENRTERMS=
GENRCONST=
#
# Capgen pax command and .so files
#
COEFF="Y"
CAPCMD="${RCXBIN}/paxfile_coeff"
CAPSO="${RCXBIN}/cap.so"
LVSFILE="${RCXBIN}/lvsfile"
#
# Do not modify the following flags
#
CAP_SW3D="N"
CAP_CN3D="N"
#
# If CAP_CORRECTION=Y, material which forms
# canonical capacitors was included in parasitic
# extraction (subtract canonical capacitance from
# parasitic capacitance to avoid double counting)
#
CAP_CORRECTION="N"
RESMODELNAME="N"
NO_CAP_CORRECTION="N"
CANONICAL_RES_CAPS="Y"
EXTRACT_MOS_DIFFUSION_AP_NW="N"
AP_SCALE_FACTOR=
CDL="N"
NEWPATTERN="Y"
NEBULASCALE=
#
# Variables for virtual metal fill
VMFCONN=
VMFFSEP=
VMFLAYERS=
VMFSSEPMAX=
VMFSSEPMIN=
VMFTYPE=
VMFWIDTH=
#
CONFORMAL="N"
#
LENGTH_UNITS="meters"
BLOCKINGLAYERS="JVARNF_DIODE_926:1,sub,diff,mt1 JVARW40_DIODE_935:1,sub,diff,mt1"
CAPGROUNDLAYER="PSUB"
EXCLUDEGATERES="Y"
CAPS2DVERSION="* caps2d version: 10"
QRCTECHFILEVERSION=
#
# CAPGENOPTS - command-line options used to generate the run-specific
#              RCXspiceINIT/RCXdspfINIT data files
#
CAPGENOPTS="-C -blocking JVARNF:1,sub,diff,mt1 -blocking JVARW40:1,sub,diff,mt1 -p poly,allGate,diff -canonical_res_caps -length_units meters -exclude_gate_res -cap_ground_layer PSUB -lvs lvsfile -p2lvs p2lvsfile ."
#
# END: Initializations
#------------------------------------------
