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m255 K3 13 cModel Technology Z0 dC:\FPGA\VERILOG\BLINK valtufm_osc0_altufm_osc_1p3 !s100 SdoFR8?i_S[8?K2=X4MfL3 Ia]WglBW2b@mYm8KX_<D1R3 Z1 V6XS1[CHT`oe?Dk`GI0;;U1 Z2 dC:\FPGA\VERILOG\LED Z3 w1194857966 Z4 8C:/FPGA/VERILOG/LED/test_led_blink.v Z5 FC:/FPGA/VERILOG/LED/test_led_blink.v L0 38 Z6 OE;L;10.0b;49 r1 !s85 0 31 Z7 !s108 1311022488.520000 Z8 !s107 C:/FPGA/VERILOG/LED/test_led_blink.v| Z9 !s90 -reportprogress|300|-work|work|-vopt|-nocovercells|C:/FPGA/VERILOG/LED/test_led_blink.v| Z10 !s102 -nocovercells Z11 o-work work -nocovercells -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPF vdivider Z12 I0H`WIJ^gTM10PBM=<ll1F0 Z13 VzE0gKI94Vd6dioZ<V:W0R1 R2 Z14 w1194858020 Z15 8C:/FPGA/VERILOG/LED/led_blink.v Z16 FC:/FPGA/VERILOG/LED/led_blink.v L0 85 R6 r1 31 Z17 !s108 1311022488.035000 Z18 !s107 C:/FPGA/VERILOG/LED/led_blink.v| Z19 !s90 -reportprogress|300|-work|work|-vopt|-nocovercells|C:/FPGA/VERILOG/LED/led_blink.v| R10 R11 Z20 !s100 B<D`MXa2o9jokOz;nCkW52 !s85 0 vled_blink Z21 IkJYnGZ4930fSBaLER73bb0 Z22 Vk;5:[AL`3Y8GjcQmimG0N3 R2 R14 R15 R16 L0 7 R6 r1 31 R17 R18 R19 R10 R11 Z23 !s100 Q1FN6dO=F98:Bh^NZO7SQ1 !s85 0 vtest_led_blink !s100 5P43G3Q:f@i`8FAKLiI:`1 IehEAGfOX]TbaQ<3`g5TdC2 Vf_D:oV8OlCEagNBIzSWSN3 R2 R3 R4 R5 L0 8 R6 r1 !s85 0 31 R7 R8 R9 R10 R11