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http://www.xilinx.com/itp/3_1i/data/fise/xst/chap02/xst02005.htm

module clock (input CCLK, input [31:0] clkscale, output reg clk);
// CCLK master crystal clock oscillator 50 MHz
reg [31:0] clkq = 0; // clock register, initial value of 0

always@(posedge CCLK)
	
		begin
			clkq = clkq + 1; // increment clock register
			if (clkq >= clkscale) // clock scaling
			   begin
			   	clk = ~clk; // output clock
				clkq = 0; // reset clock register
			   end
		end
endmodule

module clocktest (input CCLK, output LD0, LD1, LD2);

clock M0 (CCLK, 25000000, LD0); // 1 Hz clock
	clock M1 (CCLK, 12500000, LD1); // 2 Hz clock
	clock M2 (CCLK, 6250000, LD2); // 4 Hz clock

endmodule

module pbdebounce (input clk, input button, output reg pbreg);
reg [3:0] pbshift;
always@(posedge clk) // local clock event driven
begin
pbshift = pbshift << 1; // shift register
pbshift[0] = button; // read button
if (pbshift == 0) // if a bounce occurs
pbreg = 0; // clear the register
if (pbshift == 15) // 15 local clock tics without a bounce
pbreg = 1; // sets the register
end
endmodule

module counter
(
	clk,
	reset,
	result,
	ena
);

input clk;
	input reset;
	input ena;
	output [7:0] result;

reg [7:0] result;

always @(posedge clk or posedge reset)
	begin
		if (reset) 
			result = 0;		
		else if (ena) 
			result = result + 1;
	end
endmodule

reg clock, A, B;
initial
begin
clock = 0;
A = 0;
B = 1;
#11 A = 1;
#10 B = 0; A = 0;
end
always
#5 clock = ~clock;