.ALIASES
L_L1            L1(1=N11862 2=N17207 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):I10289@CLASS.L.Normal(chips)
V_V2            V2(+=VCC -=0 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):I10257@CLASS.VDC.Normal(chips)
V_V6            V6(+=RAMPE -=0 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):I10435@CLASS.Vramp.Normal(chips)
E_DIFF2          DIFF2(OUT=N10381 IN2=ERREUR IN1=RAMPE ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):I10023@ABM.DIFF.Normal(chips)
E_GLIMIT2          GLIMIT2(OUT=CONTROLE IN=N10381 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):I10173@ABM.GLIMIT.Normal(chips)
V_CONST1          CONST1(OUT=N10645 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):I10085@ABM.CONST.Normal(chips)
X_S1    S1(1=CONTROLE 2=0 3=N11862 4=VCC ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):I10217@BREAKOUT.Sbreak.Normal(chips)
E_DIFF1          DIFF1(OUT=N10187 IN2=N10645 IN1=BOUCLE ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):I10491@ABM.DIFF.Normal(chips)
E_GLIMIT1          GLIMIT1(OUT=ERREUR IN=N10187 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):I10133@ABM.GLIMIT.Normal(chips)
V_V7            V7(+=N17254 -=0 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):INS16751@CLASS.VDC.Normal(chips)
R_R1            R1(1=N17662 2=BOUCLE ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):INS17436@CLASS.R.Normal(chips)
C_C1            C1(1=BOUCLE 2=0 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):INS17498@CLASS.C.Normal(chips)
C_C2            C2(1=0 2=N22671 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):INS22450@ANALOG.C.Normal(chips)
R_R2            R2(1=0 2=N22671 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):INS22475@ANALOG.R.Normal(chips)
L_L2            L2(1=N22602 2=N22671 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):INS22500@ANALOG.L.Normal(chips)
V_V8            V8(+=N22602 -=0 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):INS22562@SOURCE.VPULSE.Normal(chips)
M_M1            M1(d=N23410 g=N23860 s=N23439 s=N23439 ) CN @BUCK MODE
+TEST.SCHEMATIC1(sch_1):INS23165@BREAKOUT.MbreakN3.Normal(chips)
L_L3            L3(1=N23439 2=N23548 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):INS23221@ANALOG.L.Normal(chips)
V_V3            V3(+=N23410 -=0 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):INS23305@CLASS.VDC.Normal(chips)
C_C3            C3(1=0 2=N23548 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):INS23506@ANALOG.C.Normal(chips)
R_R3            R3(1=0 2=N23548 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):INS23532@ANALOG.R.Normal(chips)
V_V9            V9(+=N23860 -=N23439 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):INS23662@SOURCE.VPULSE.Normal(chips)
C_C4            C4(1=0 2=N25888 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):INS25191@ANALOG.C.Normal(chips)
V_V4            V4(+=N25169 -=0 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):INS25135@CLASS.VDC.Normal(chips)
R_R4            R4(1=0 2=TOTO ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):INS25215@ANALOG.R.Normal(chips)
R_R5            R5(1=N25888 2=TOTO ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):INS25550@ANALOG.R.Normal(chips)
R_R6            R6(1=N25873 2=N25173 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):INS25576@ANALOG.R.Normal(chips)
R_R7            R7(1=N25948 2=N25169 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):INS25604@ANALOG.R.Normal(chips)
M_M3            M3(d=N25948 g=N260171 s=N25173 s=N25173 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):INS26005@PWRMOS.IRF150.Normal(chips)
D_D4            D4(1=0 2=N25173 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):INS26054@DIODE.MBR360.Normal(chips)
R_R8            R8(1=N260171 2=N25848 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):INS26189@ANALOG.R.Normal(chips)
R_R9            R9(1=N25173 2=N25848 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):INS26247@ANALOG.R.Normal(chips)
V_V11           V11(+=N25848 -=N25173 ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):INS26925@SOURCE.VPULSE.Normal(chips)
L_L5            L5(1=N25873 2=TOTO ) CN @BUCK MODE TEST.SCHEMATIC1(sch_1):INS27331@ANALOG_P.l.Normal(chips)
_    _(BOUCLE=BOUCLE)
_    _(controle=CONTROLE)
_    _(Erreur=ERREUR)
_    _(Rampe=RAMPE)
_    _(toto=TOTO)
_    _(Vcc=VCC)
.ENDALIASES