.ALIASES
E_E1            E1(3=N00114 4=0 1=N00298 2=0 ) CN @BUCKAVG.SCHEMATIC1(sch_1):I00003@ANALOG.E.Normal(chips)
D_D2            D2(1=0 2=N01595 ) CN @BUCKAVG.SCHEMATIC1(sch_1):I01453@BREAKOUT.Dbreak.Normal(chips)
R_R4            R4(1=N014311 2=0 ) CN @BUCKAVG.SCHEMATIC1(sch_1):I06033@ANALOG.R.Normal(chips)
V_V3            V3(+=INPUT -=0 ) CN @BUCKAVG.SCHEMATIC1(sch_1):I00014@SOURCE.VDC.Normal(chips)
R_R2            R2(1=0 2=OUTPUT ) CN @BUCKAVG.SCHEMATIC1(sch_1):I00036@ANALOG.R.Normal(chips)
C_C1            C1(1=N00573 2=N06685 ) CN @BUCKAVG.SCHEMATIC1(sch_1):I00529@ANALOG.C.Normal(chips)
R_R1            R1(1=N00573 2=0 ) CN @BUCKAVG.SCHEMATIC1(sch_1):I00551@ANALOG.R.Normal(chips)
D_D3            D3(1=N00270 2=N05648 ) CN @BUCKAVG.SCHEMATIC1(sch_1):I05626@BREAKOUT.Dbreak.Normal(chips)
V_V2            V2(+=CONTROL -=0 ) CN @BUCKAVG.SCHEMATIC1(sch_1):I00088@SOURCE.VPULSE.Normal(chips)
X_S2    S2(1=CONTROL 2=0 3=INPUT 4=N01595 ) CN @BUCKAVG.SCHEMATIC1(sch_1):I02995@BREAKOUT.Sbreak.Normal(chips)
R_R3            R3(1=N06685 2=0 ) CN @BUCKAVG.SCHEMATIC1(sch_1):I05946@ANALOG.R.Normal(chips)
V_V1            V1(+=N00298 -=0 ) CN @BUCKAVG.SCHEMATIC1(sch_1):I00414@SOURCE.VDC.Normal(chips)
L_L2            L2(1=N01595 2=OUTPUT ) CN @BUCKAVG.SCHEMATIC1(sch_1):I01409@ANALOG.L.Normal(chips)
X_F1    F1(1=N00114 2=N00270 3=N00298 4=N00114 ) CN @BUCKAVG.SCHEMATIC1(sch_1):I00943@ANALOG.F.Normal(chips)
C_C2            C2(1=OUTPUT 2=N014311 ) CN @BUCKAVG.SCHEMATIC1(sch_1):I01431@ANALOG.C.Normal(chips)
L_L1            L1(1=N05648 2=N00573 ) CN @BUCKAVG.SCHEMATIC1(sch_1):I00470@ANALOG.L.Normal(chips)
_    _(Control=CONTROL)
_    _(Input=INPUT)
_    _(Output=OUTPUT)
.ENDALIASES