* source BUCK SCC
D_D1         0 N08291 Dbreak 
V_Vs         INPUT 0 5
R_R1         0 OUTPUT  1k  
V_V1         CONTROL 0  
+PULSE 0 5 0 1n 1n {Duty/Freq} {1/Freq}
X_S2    N08197 0 N05450 OUTPUT SCHEMATIC1_S2 
X_S1    CONTROL 0 INPUT N05450 SCHEMATIC1_S1 
D_D2         N08291 OUTPUT Dbreak 
V_V2         N08197 0  
+PULSE 0 5 {0.5/Freq} 1n 1n {Duty/Freq} {1/Freq}
C_C2         0 OUTPUT  10u IC=0 
C_C1         N05450 N08291  10u IC=0 
.PARAM  duty=.4 freq=100k

.subckt SCHEMATIC1_S2 1 2 3 4  
S_S2         3 4 1 2 Sbreak
RS_S2         1 2 1G
.ends SCHEMATIC1_S2

.subckt SCHEMATIC1_S1 1 2 3 4  
S_S1         3 4 1 2 Sbreak
RS_S1         1 2 1G
.ends SCHEMATIC1_S1