* source INVERTER
D_D1         OUTPUT N05257 Dbreak 
V_Vs         INPUT 0 5
R_R1         0 OUTPUT  1k  
V_V1         CONTROL 0  
+PULSE 0 5 0 10n 10n {Duty/Freq} {1/Freq}
X_S2    N05593 0 N05432 0 SCHEMATIC1_S2 
X_S1    CONTROL 0 INPUT N05432 SCHEMATIC1_S1 
R_Resr         0 N014311  15m  
D_D2         N05257 0 Dbreak 
V_V2         N05593 0  
+PULSE 0 5 {0.5/Freq} 10n 10n {Duty/Freq} {1/Freq}
C_C2         N05432 N05257  10u  
C_C1         OUTPUT N014311  10u  
.PARAM  duty=.4 freq=100k

.subckt SCHEMATIC1_S2 1 2 3 4  
S_S2         3 4 1 2 Sbreak
RS_S2         1 2 1G
.ends SCHEMATIC1_S2

.subckt SCHEMATIC1_S1 1 2 3 4  
S_S1         3 4 1 2 Sbreak
RS_S1         1 2 1G
.ends SCHEMATIC1_S1