.ALIASES
M_M6            M6(d=N269406 g=N269406 s=0 b=0 ) CN @CHAPTER 6.Design 1 and 2(sch_1):I269442@SEDRA_LIB.NMOS0P5.Normal(chips)
C_C3            C3(1=0 2=N269576 ) CN @CHAPTER 6.Design 1 and 2(sch_1):I269686@ANALOG.C.Normal(chips)
R_R2            R2(1=N240102 2=N240298 ) CN @CHAPTER 6.Design 1 and 2(sch_1):I240288@ANALOG.R.Normal(chips)
M_M7            M7(d=N269250 g=N269250 s=VDD b=VDD ) CN @CHAPTER 6.Design 1 and 2(sch_1):I269216@SEDRA_LIB.PMOS0P5.Normal(chips)
M_M3            M3(d=N239844 g=N239844 s=VDD b=VDD ) CN @CHAPTER 6.Design 1 and 2(sch_1):I239814@SEDRA_LIB.PMOS0P5.Normal(chips)
C_C1            C1(1=0 2=N239856 ) CN @CHAPTER 6.Design 1 and 2(sch_1):I240078@ANALOG.C.Normal(chips)
I_I1            I1(+=VDD -=N269406 ) CN @CHAPTER 6.Design 1 and 2(sch_1):I269484@SOURCE.IDC.Normal(chips)
I_I2            I2(+=N239844 -=0 ) CN @CHAPTER 6.Design 1 and 2(sch_1):I240326@SOURCE.IDC.Normal(chips)
V_Vsig1          Vsig1(+=N269702 -=0 ) CN @CHAPTER 6.Design 1 and 2(sch_1):I269734@SOURCE.VAC.Normal(chips)
I_I3            I3(+=N269256 -=0 ) CN @CHAPTER 6.Design 1 and 2(sch_1):I269278@SOURCE.IDC.Normal(chips)
C_C4            C4(1=0 2=OUT2 ) CN @CHAPTER 6.Design 1 and 2(sch_1):I270020@ANALOG.C.Normal(chips)
M_M1            M1(d=OUT1 g=N240298 s=N239856 b=0 ) CN @CHAPTER 6.Design 1 and 2(sch_1):I239898@SEDRA_LIB.NMOS0P5.Normal(chips)
I_I5            I5(+=N269328 -=0 ) CN @CHAPTER 6.Design 1 and 2(sch_1):I269542@SOURCE.IDC.Normal(chips)
I_I6            I6(+=N269576 -=0 ) CN @CHAPTER 6.Design 1 and 2(sch_1):I269786@SOURCE.IDC.Normal(chips)
V_Vsig          Vsig(+=N240102 -=0 ) CN @CHAPTER 6.Design 1 and 2(sch_1):I240148@SOURCE.VAC.Normal(chips)
R_R3            R3(1=N269702 2=N269822 ) CN @CHAPTER 6.Design 1 and 2(sch_1):I269812@ANALOG.R.Normal(chips)
M_M11           M11(d=D g=N269822 s=N269576 b=0 ) CN @CHAPTER 6.Design 1 and 2(sch_1):I270072@SEDRA_LIB.NMOS0P5.Normal(chips)
M_M4            M4(d=OUT2 g=N269256 s=D b=VDD ) CN @CHAPTER 6.Design 1 and 2(sch_1):I269108@SEDRA_LIB.PMOS0P5.Normal(chips)
C_C2            C2(1=0 2=OUT1 ) CN @CHAPTER 6.Design 1 and 2(sch_1):I240196@ANALOG.C.Normal(chips)
M_M2            M2(d=OUT1 g=N239844 s=VDD b=VDD ) CN @CHAPTER 6.Design 1 and 2(sch_1):I239960@SEDRA_LIB.PMOS0P5.Normal(chips)
M_M9            M9(d=D g=N269328 s=VDD b=VDD ) CN @CHAPTER 6.Design 1 and 2(sch_1):I269622@SEDRA_LIB.PMOS0P5.Normal(chips)
M_M5            M5(d=N269328 g=N269328 s=VDD b=VDD ) CN @CHAPTER 6.Design 1 and 2(sch_1):I269384@SEDRA_LIB.PMOS0P5.Normal(chips)
M_M8            M8(d=N269256 g=N269256 s=N269250 b=VDD ) CN @CHAPTER 6.Design 1 and
+2(sch_1):I269162@SEDRA_LIB.PMOS0P5.Normal(chips)
M_M10           M10(d=OUT2 g=N269406 s=0 b=0 ) CN @CHAPTER 6.Design 1 and 2(sch_1):I269890@SEDRA_LIB.NMOS0P5.Normal(chips)
I_I4            I4(+=N239856 -=0 ) CN @CHAPTER 6.Design 1 and 2(sch_1):I240262@SOURCE.IDC.Normal(chips)
V_V2            V2(+=VDD -=0 ) CN @CHAPTER 6.Design 1 and 2(sch_1):I240032@SOURCE.VDC.Normal(chips)
_    _(OUT2=OUT2)
_    _(OUT1=OUT1)
_    _(VDD=VDD)
_    _(VDD=VDD)
_    _(D=D)
.ENDALIASES