.ALIASES
R_R2            R2(1=N227421 2=IN ) CN @CHAPTER 6.Design 1(sch_1):I38081@ANALOG.R.Normal(chips)
M_M1            M1(d=OUT g=IN s=N227257 b=0 ) CN @CHAPTER 6.Design 1(sch_1):I00736@SEDRA_LIB.NMOS0P5.Normal(chips)
V_V2            V2(+=VDD -=0 ) CN @CHAPTER 6.Design 1(sch_1):I239596@SOURCE.VDC.Normal(chips)
I_I4            I4(+=N227257 -=0 ) CN @CHAPTER 6.Design 1(sch_1):I231657@SOURCE.IDC.Normal(chips)
M_M3            M3(d=N203941 g=N203941 s=VDD b=VDD ) CN @CHAPTER 6.Design 1(sch_1):I220094@SEDRA_LIB.PMOS0P5.Normal(chips)
C_C1            C1(1=0 2=N227257 ) CN @CHAPTER 6.Design 1(sch_1):I227093@ANALOG.C.Normal(chips)
M_M2            M2(d=OUT g=N203941 s=VDD b=VDD ) CN @CHAPTER 6.Design 1(sch_1):I199898@SEDRA_LIB.PMOS0P5.Normal(chips)
V_Vsig          Vsig(+=N227421 -=0 ) CN @CHAPTER 6.Design 1(sch_1):I203869@SOURCE.VAC.Normal(chips)
I_I2            I2(+=N203941 -=0 ) CN @CHAPTER 6.Design 1(sch_1):I220018@SOURCE.IDC.Normal(chips)
C_C2            C2(1=0 2=OUT ) CN @CHAPTER 6.Design 1(sch_1):I204124@ANALOG.C.Normal(chips)
_    _(OUT=OUT)
_    _(VDD=VDD)
_    _(IN=IN)
.ENDALIASES