.ALIASES
M_M5            M5(d=OUT g=N204088 s=0 b=0 ) CN @CHAPTER 6.Design 2(sch_1):I203413@SEDRA_LIB.NMOS0P5.Normal(chips)
C_C2            C2(1=0 2=N238675 ) CN @CHAPTER 6.Design 2(sch_1):I238855@ANALOG.C.Normal(chips)
M_M7            M7(d=N260143 g=N260143 s=VDD b=VDD ) CN @CHAPTER 6.Design 2(sch_1):I260063@SEDRA_LIB.PMOS0P5.Normal(chips)
I_I3            I3(+=N260214 -=0 ) CN @CHAPTER 6.Design 2(sch_1):I260315@SOURCE.IDC.Normal(chips)
M_M2            M2(d=OUT g=N260214 s=D b=VDD ) CN @CHAPTER 6.Design 2(sch_1):I259868@SEDRA_LIB.PMOS0P5.Normal(chips)
V_Vsig          Vsig(+=N238879 -=0 ) CN @CHAPTER 6.Design 2(sch_1):I238925@SOURCE.VAC.Normal(chips)
I_I2            I2(+=N225156 -=0 ) CN @CHAPTER 6.Design 2(sch_1):I225456@SOURCE.IDC.Normal(chips)
M_M4            M4(d=N225156 g=N225156 s=VDD b=VDD ) CN @CHAPTER 6.Design 2(sch_1):I225216@SEDRA_LIB.PMOS0P5.Normal(chips)
M_M1            M1(d=D g=IN s=N238675 b=0 ) CN @CHAPTER 6.Design 2(sch_1):I238717@SEDRA_LIB.NMOS0P5.Normal(chips)
C_C1            C1(1=0 2=OUT ) CN @CHAPTER 6.Design 2(sch_1):I204271@ANALOG.C.Normal(chips)
M_M8            M8(d=N260214 g=N260214 s=N260143 b=VDD ) CN @CHAPTER 6.Design 2(sch_1):I259981@SEDRA_LIB.PMOS0P5.Normal(chips)
M_M6            M6(d=N204088 g=N204088 s=0 b=0 ) CN @CHAPTER 6.Design 2(sch_1):I225278@SEDRA_LIB.NMOS0P5.Normal(chips)
M_M3            M3(d=D g=N225156 s=VDD b=VDD ) CN @CHAPTER 6.Design 2(sch_1):I238779@SEDRA_LIB.PMOS0P5.Normal(chips)
I_I4            I4(+=N238675 -=0 ) CN @CHAPTER 6.Design 2(sch_1):I239021@SOURCE.IDC.Normal(chips)
R_R2            R2(1=N238879 2=IN ) CN @CHAPTER 6.Design 2(sch_1):I239047@ANALOG.R.Normal(chips)
V_V2            V2(+=VDD -=0 ) CN @CHAPTER 6.Design 2(sch_1):I255447@SOURCE.VDC.Normal(chips)
I_I1            I1(+=VDD -=N204088 ) CN @CHAPTER 6.Design 2(sch_1):I225326@SOURCE.IDC.Normal(chips)
_    _(IN=IN)
_    _(D=D)
_    _(VDD=VDD)
_    _(OUT=OUT)
.ENDALIASES