* source PORTE
U_DSTM1         STIM(1,1) $G_DPWR $G_DGND IN IO_STM IO_LEVEL=0 
+ 0 0
+ +5uS 1
+REPEAT FOREVER
+ +5uS 0
+  +5uS 1
+ ENDREPEAT
X_U6A         Q2 Q0 $G_DPWR $G_DGND 7404 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U7A         N02208 N02245 $G_DPWR $G_DGND 7404 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U2A         IN Q3 N02423 $G_DPWR $G_DGND 7402 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
V_V1         VDD 0  DC 2.5V
X_U8A         N02245 Q3 $G_DPWR $G_DGND 7404 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
V_V2         VSS 0  DC -2.5V
X_U9A         Q3 Q1 $G_DPWR $G_DGND 7404 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U3A         Q2 N02168 N02208 $G_DPWR $G_DGND 7402 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U10A         IN N02168 $G_DPWR $G_DGND 7404 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U1A         IN OUT $G_DPWR $G_DGND 7404 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U4A         N02423 N02460 $G_DPWR $G_DGND 7404 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U5A         N02460 Q2 $G_DPWR $G_DGND 7404 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0