m255
K3
13
cModel Technology
Z0 dC:\modeltech_6.5\examples\tutorials\verilog\projects
T_opt
Z1 VRJM?:T;@JHl?zBa564gUK2
Z2 04 12 4 work test_counter fast 0
Z3 =1-080027003811-4e19678d-fa-b3c
Z4 o-quiet -auto_acc_if_foreign -work work
Z5 n@_opt
Z6 OE;O;6.5;42
vcounter
Z7 IcYjT31i3?R^:bIIUiBQXL0
Z8 Ve:VQh7zF_VJYN9MbEXUG_3
Z9 dC:\Verilog\02
Z10 w1232696185
Z11 8C:/Verilog/02/counter.v
Z12 FC:/Verilog/02/counter.v
L0 10
Z13 OE;L;6.5;42
r1
31
Z14 !s102 -nocovercells
Z15 o-work work -nocovercells -L mtiAvm -L mtiOvm -L mtiUPF
Z16 !s100 a3UkEohc2S8KTmdVT8[S82
!s85 0
vtest_counter
Z17 IA70aBgg_X_H1]3KCB^aB[3
Z18 V>T;oP;DmM7QBG7>?_7Qjl1
R9
R10
Z19 8C:/Verilog/02/tcounter.v
Z20 FC:/Verilog/02/tcounter.v
L0 10
R13
r1
31
R15
R14
Z21 !s100 K4XU44W89M1:lzWUiT@0`0
!s85 0