m255
K3
13
cModel Technology
Z0 dC:\modeltech_6.5\examples\tutorials\verilog\projects
T_opt
Z1 VRJM?:T;@JHl?zBa564gUK2
Z2 04 12 4 work test_counter fast 0
Z3 =1-080027003811-4e19678d-fa-b3c
Z4 o-quiet -auto_acc_if_foreign -work work
Z5 n@_opt
Z6 OE;O;6.5;42
T_opt1
Z7 VQKWKb7WT5A7L>hhC@Y37:2
Z8 04 18 4 work Counter4_TESTBENCH fast 0
Z9 =1-080027003811-4e196954-3c8-1b0
R4
Z10 n@_opt1
R6
vcounter
Z11 IcYjT31i3?R^:bIIUiBQXL0
Z12 Ve:VQh7zF_VJYN9MbEXUG_3
Z13 dC:\Verilog\02
Z14 w1232696185
Z15 8C:/Verilog/02/counter.v
Z16 FC:/Verilog/02/counter.v
L0 10
Z17 OE;L;6.5;42
r1
31
Z18 !s102 -nocovercells
Z19 o-work work -nocovercells -L mtiAvm -L mtiOvm -L mtiUPF
Z20 !s100 a3UkEohc2S8KTmdVT8[S82
!s85 0
vCounter4
Z21 I2iBf?::oDej[00g:A;gg72
Z22 Vk<XHIhajB7UfGg<S_KJ3b1
R13
Z23 w1310288061
Z24 8C:/Verilog/02/seq4.v
Z25 FC:/Verilog/02/seq4.v
L0 3
R17
r1
31
R18
R19
Z26 n@counter4
Z27 !s100 <VWM]`6L9=mgF_zERl@>?0
!s85 0
vCounter4_TESTBENCH
Z28 IB9F^7J4STECCoLlIEYN4h3
Z29 V84GDPHTL9zPCmo`FjWabH0
R13
Z30 w1310288066
Z31 8C:/Verilog/02/seq4_tb.v
Z32 FC:/Verilog/02/seq4_tb.v
L0 7
R17
r1
31
R18
R19
Z33 n@counter4_@t@e@s@t@b@e@n@c@h
Z34 !s100 GViKGh@GJA6:Y4HE4kQUn2
!s85 0
vtest_counter
Z35 IA70aBgg_X_H1]3KCB^aB[3
Z36 V>T;oP;DmM7QBG7>?_7Qjl1
R13
R14
Z37 8C:/Verilog/02/tcounter.v
Z38 FC:/Verilog/02/tcounter.v
L0 10
R17
r1
31
R19
R18
Z39 !s100 K4XU44W89M1:lzWUiT@0`0
!s85 0
