library verilog;
use verilog.vl_types.all;
entity Counter4 is
    port(
        \i$Clock\       : in     vl_logic;
        \i$Reset\       : in     vl_logic;
        \i$InializeCount\: in     vl_logic;
        \i$CountUp\     : in     vl_logic;
        \i$EnableCount\ : in     vl_logic;
        \i$N\           : in     vl_logic_vector(3 downto 0);
        \o$Count\       : out    vl_logic_vector(7 downto 0);
        \o$AtMidpoint\  : out    vl_logic
    );
end Counter4;