library verilog;
use verilog.vl_types.all;
entity Frequency_Divider is
    generic(
        Divisor         : integer := 4;
        Bits            : integer := 2
    );
    port(
        i_Clock         : in     vl_logic;
        i_Reset         : in     vl_logic;
        o_Out           : out    vl_logic
    );
end Frequency_Divider;