module counter(clk,rst,s);
input clk; //define ports
input rst;
output[3:0] s;

reg[3:0] s;
always @ (posedge clk or negedge rst)
if (!rst) //asyn rst
 s <= 0;
else begin //rising edge of clk
if(s==9) //overflow
s <= 4'b0;
else //increment
 s <= s+1;
end
endmodule