m255
K3
13
cModel Technology
Z0 dC:\VHDL\Clavier
T_opt
Z1 VLGfa1gGNTE49X8[9o9[>C3
Z2 04 7 4 work counter fast 0
Z3 =1-080027003811-4e18bcae-1a5-1424
Z4 o-quiet -auto_acc_if_foreign -work work
Z5 n@_opt
Z6 OE;O;6.5;42
T_opt1
Z7 V2LB603E<:B[37GT;k4][[3
Z8 04 16 4 work first_counter_tb fast 0
Z9 =1-080027003811-4e18bff8-2ce-1374
R4
Z10 n@_opt1
R6
vcounter
Z11 IndO8^=c8jzjW0QPhQSkjJ1
Z12 V2fbo=EmEPeHL_1C61ElPG2
Z13 dC:\Verilog\CPT
Z14 w1310243953
Z15 8C:/Verilog/CPT/horloge.v
Z16 FC:/Verilog/CPT/horloge.v
L0 1
Z17 OE;L;6.5;42
r1
31
Z18 o-work work -nocovercells -L mtiAvm -L mtiOvm -L mtiUPF
Z19 !s102 -nocovercells
Z20 !s100 Z_;B`8OoOkmzVV0:_ejXS0
!s85 0
vfirst_counter
Z21 IP9nC9FzZiWO2[PonR7RmU2
Z22 VGMIYGl0i:6:Tm:bfObkLD3
R13
Z23 w1310244805
Z24 Fcpt.v
Z25 8C:/Verilog/CPT/bench.v
Z26 FC:/Verilog/CPT/bench.v
L0 9
R17
r1
31
R19
R18
Z27 !s100 g7VEDOX7Ga_7P:Al0?OMO2
!s85 0
vfirst_counter_tb
Z28 I]J677f`;n_mKJ8S[CVdRn0
Z29 ViHACe[nSZM`Il0bkK_E5j2
R13
R23
R25
R26
L0 2
R17
r1
31
R19
R18
Z30 !s100 hz6<>XeTn3?HXjMWDo1de3
!s85 0