m255
K3
13
cModel Technology
Z0 dD:\modeltech_10.0b\examples
T_opt
Z1 V<8F]j6f^i:EjozPZd^BZe0
Z2 04 10 4 work test_adder fast 0
Z3 =1-002215fd5ab9-4e2313c7-196-12b0
Z4 o-quiet -auto_acc_if_foreign -work work +acc
Z5 n@_opt
Z6 OE;O;10.0b;49
Z7 dD:\modeltech_10.0b\examples
vfull_adder
Z8 IKz3h`k?VXFM;QU1i_zbNg3
Z9 VDXIz@A8ZlZIe0^?_MInkU1
Z10 dC:\PATRICE\Verilog\TP5
Z11 w1310921479
Z12 8C:\PATRICE\Verilog\TP5\full_adder.v
Z13 FC:\PATRICE\Verilog\TP5\full_adder.v
L0 1
Z14 OE;L;10.0b;49
r1
31
Z15 !s102 -nocovercells
Z16 o-work work -nocovercells -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPF
Z17 !s100 ]Gh2A:WlXJ]`1>Z2J[bDg1
Z18 !s108 1310921617.249000
Z19 !s107 C:\PATRICE\Verilog\TP5\full_adder.v|
Z20 !s90 -reportprogress|300|-work|work|-vopt|-nocovercells|C:\PATRICE\Verilog\TP5\full_adder.v|
!s85 0
vfull_adder_4bit
Z21 IED94d6n8k6<PH7NaNMAdo2
Z22 VKHUmFeScX:?S1C^[SSMVU0
R10
Z23 w1310921544
Z24 8C:/PATRICE/Verilog/TP5/full_adder_4bit.v
Z25 FC:/PATRICE/Verilog/TP5/full_adder_4bit.v
L0 1
R14
r1
31
R15
R16
Z26 !s90 -reportprogress|300|-work|work|-vopt|-nocovercells|C:/PATRICE/Verilog/TP5/full_adder_4bit.v|
Z27 !s100 NJaFfIh<:c7AbKKLac2an3
!s85 0
Z28 !s108 1310921617.546000
Z29 !s107 C:/PATRICE/Verilog/TP5/full_adder_4bit.v|
vtest_adder
Z30 IURaV3@47zUCWMe51`F3MO0
Z31 Vkh4:d`02zlKN@aXMYoZ@J1
R10
Z32 w1310921596
Z33 8C:\PATRICE\Verilog\TP5\test_adder.v
Z34 FC:\PATRICE\Verilog\TP5\test_adder.v
L0 1
R14
r1
31
R15
R16
Z35 !s100 :kE33nkE;Zk8jdHdhK`KE3
Z36 !s108 1310921616.890000
Z37 !s107 C:\PATRICE\Verilog\TP5\test_adder.v|
Z38 !s90 -reportprogress|300|-work|work|-vopt|-nocovercells|C:\PATRICE\Verilog\TP5\test_adder.v|
!s85 0