// 2^25 = 50MHz

module hz (
clock ,  
h  
);

input clock; //Master Clock 50 MHz
output h;

reg [24:0]CLKQ; //clock divider register
reg h;

always@(posedge clock)
begin
CLKQ<=CLKQ+1; //clock divider register
if (CLKQ==25000000) //1 Hz Output Clock: 50 MHz Master
begin // Clock 25x10^6 half-cycle count
h=~h; //Output Clock
CLKQ<=0; //reset clock divider register
end
end


endmodule

///////////////////////////////////////////////////////

module clock_diviseur(clock, reset, clk_seconde, clk_minute);

   input clock, reset;
   output reg clk_seconde;
   output reg clk_minute; 
  
   parameter diviseur =  10 ; //25000000;
   reg[24:0] compteur_secondes;
   reg[24:0] compteur_minutes;
   reg ClkInt;
   wire reset;
	
	  always @(posedge clock) begin
      if( reset == 1 )begin
         compteur_secondes <= 0;
         clk_minute <= 0;
         clk_seconde <= 0;
         ClkInt <= 0;
      end
      else begin
         if( compteur_secondes == diviseur ) begin
            clk_seconde <= ~ClkInt;
            ClkInt <= ~ClkInt;
            compteur_secondes <= 0;
         end
         else begin
            clk_seconde <= ClkInt;
            ClkInt <= ClkInt;
            compteur_secondes <= compteur_secondes + 1;
         end
         
  
         if( compteur_secondes == 60 ) begin
            compteur_minutes <= 0; 
              clk_minute <= ~clk_minute ; 
         end
         else begin
           clk_minute <= clk_minute ;
           compteur_minutes <= compteur_minutes +1;
         end  
   
         //else begin
         //   ClkOut <= ClkInt;
         //   ClkInt <= ClkInt;
         //   minutes <= minutes + 1;
         //end
         
         
         
     end  
         
         
      
   end
endmodule

////////////////////////////////////////////////////////  

module compteur (
clock , // Clock input of the design
reset , // active high, synchronous Reset input
enable , // Active high enable signal for counter
counter_out, // 4 bit vector output of the counter
); // End of port list

//-------------Input Ports-----------------------------
input clock ;
input reset ;
input enable ;

//-------------Output Ports----------------------------
output [3:0] counter_out ;

//-------------Input ports Data Type-------------------
wire clock ;
wire reset ;
wire enable ;
//-------------Output Ports Data Type------------------
reg [3:0] counter_out ;

//------------Code Starts Here-------------------------
always @ (posedge clock)
begin : COUNTER // Block Name
  // At every rising edge of clock we check if reset is active
  // If active, we load the counter output with 4'b0000
  if (reset == 1'b1) begin
    counter_out <= #1 4'b0000;
  end
  // If enable is active, then we increment the counter
  else if (enable == 1'b1) begin
    counter_out <= #1 counter_out + 1;
  end
end // End of Block COUNTER

endmodule // End of Module counter 



///////////////////////////////////////////////////////
module bench_test();
// Declare inputs as regs and outputs as wires
reg clock, reset, enable;
wire [3:0] counter_out;


// Initialize all variables
initial begin        
  $display ("time\t clk reset enable counter");	
  $monitor ("%g\t %b   %b     %b      %b", 
	  $time, clock, reset, enable, counter_out);	
  clock = 1;       // initial value of clock
  reset = 0;       // initial value of reset
  enable = 0;      // initial value of enable
  
  #5 reset = 1;    // Assert the reset
  #10 reset = 0;   // De-assert the reset
  #10 enable = 1;  // Assert enable
  #100 enable = 0; // De-assert enable
  #5 $finish;      // Terminate simulation
end

// Clock generator
always begin
  #5 clock = ~clock; // Toggle clock every 5 ticks
end

// Connect DUT to test bench
compteur DUT1 (clock, reset, enable, counter_out);
hz DUT2 (clock, h);
clock_diviseur DUT3 (clock, reset, clk_second, clk_minute);

endmodule