module fb_counter_b (Q,clock,clear,enable);
output [3:0] Q;
input clock, clear, enable;
reg [3:0] Q;
reg [3:0] internal;
always @(clock or enable or clear) begin
if (~clear) internal = 0;
else if (clock & enable)
internal = internal + 1;
end
always @(negedge clock or negedge clear) begin
if (~clear) Q <= 0;
else Q <= internal;
end
endmodule
module fb_counter_tb;
reg CLK, CLR, EN;
wire [3:0] Q;
fb_counter_b i1 (.Q(Q), .clock(CLK), .clear(CLR), .enable(EN));
always #10 CLK = ~CLK;
initial begin
CLR = 0; CLK = 0; EN = 0;
#10 CLR = 1;
#13; EN = 1;
#400 CLR = 0;
#10 CLR = 1;
#400 EN = 0;
#100 EN = 1;
#50 $finish;
end
initial begin
$shm_open("two");
$shm_probe("AC");
$monitor("CLR = %b; CLK = %b; EN = %b, Q = %d",CLR, CLK, EN, Q);
end
endmodule