library verilog;
use verilog.vl_types.all;
entity digitalClock is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        dispH1          : out    vl_logic_vector(6 downto 0);
        dispH0          : out    vl_logic_vector(6 downto 0);
        dispM1          : out    vl_logic_vector(6 downto 0);
        dispM0          : out    vl_logic_vector(6 downto 0);
        dispS1          : out    vl_logic_vector(6 downto 0);
        dispS0          : out    vl_logic_vector(6 downto 0)
    );
end digitalClock;